derek.holloway
7502bf64a4
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32 lines
1.0 KiB
YAML
32 lines
1.0 KiB
YAML
# RUN: llc -mtriple=amdgcn -run-pass liveintervals -verify-machineinstrs -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s
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# RUN: llc -mtriple=amdgcn -passes='print<live-intervals>' -filetype=null -debug-only=regalloc %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# We currently maintain a main liveness range which operates like a superset of
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# all subregister liveranges. We may need to create additional SSA values at
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# merge point in this main liverange even though none of the subregister
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# liveranges needed it.
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#
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# Should see three distinct value numbers:
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# CHECK: %0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}}
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--- |
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define amdgpu_kernel void @test0() { ret void }
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...
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---
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name: test0
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registers:
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- { id: 0, class: sreg_64 }
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0
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S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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S_NOP 0, implicit-def %0.sub1
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S_NOP 0, implicit %0.sub1
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S_BRANCH %bb.2
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bb.2:
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S_NOP 0, implicit %0.sub0
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...
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