derek.holloway
7502bf64a4
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164 lines
6.2 KiB
LLVM
164 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefixes=GCN,GISEL %s
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define amdgpu_ps void @prefetch_data_sgpr_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
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; GCN-LABEL: prefetch_data_sgpr_base_sgpr_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_imm_base_sgpr_len(ptr addrspace(4) inreg %ptr, i32 inreg %len) {
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; GCN-LABEL: prefetch_data_sgpr_imm_base_sgpr_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x200, s2, 0
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; GCN-NEXT: s_endpgm
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entry:
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_base_imm_len(ptr addrspace(4) inreg %ptr) {
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; GCN-LABEL: prefetch_data_sgpr_base_imm_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_imm_base_imm_len(ptr addrspace(4) inreg %ptr) {
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; GCN-LABEL: prefetch_data_sgpr_imm_base_imm_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x200, null, 31
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; GCN-NEXT: s_endpgm
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entry:
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_data_vgpr_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
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; GCN-LABEL: prefetch_data_vgpr_base_sgpr_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_readfirstlane_b32 s2, v0
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; GCN-NEXT: v_readfirstlane_b32 s3, v1
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; GCN-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_data_vgpr_imm_base_sgpr_len(ptr addrspace(4) %ptr, i32 inreg %len) {
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; SDAG-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: v_readfirstlane_b32 s2, v0
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; SDAG-NEXT: v_readfirstlane_b32 s3, v1
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; SDAG-NEXT: s_prefetch_data s[2:3], 0x200, s0, 0
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: prefetch_data_vgpr_imm_base_sgpr_len:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: v_add_co_u32 v0, vcc_lo, 0x200, v0
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
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; GISEL-NEXT: v_readfirstlane_b32 s2, v0
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GISEL-NEXT: v_readfirstlane_b32 s3, v1
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; GISEL-NEXT: s_prefetch_data s[2:3], 0x0, s0, 0
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; GISEL-NEXT: s_endpgm
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entry:
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%gep = getelementptr i32, ptr addrspace(4) %ptr, i32 128
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %gep, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_base_vgpr_len(ptr addrspace(4) inreg %ptr, i32 %len) {
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; GCN-LABEL: prefetch_data_sgpr_base_vgpr_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_readfirstlane_b32 s2, v0
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_global(ptr addrspace(1) inreg %ptr) {
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; GCN-LABEL: prefetch_data_sgpr_base_imm_len_global:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_data_sgpr_base_imm_len_flat(ptr inreg %ptr) {
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; GCN-LABEL: prefetch_data_sgpr_base_imm_len_flat:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 31
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 31)
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ret void
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}
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define amdgpu_ps void @prefetch_data_vgpr_base_imm_len(ptr addrspace(4) %ptr) {
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; GCN-LABEL: prefetch_data_vgpr_base_imm_len:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: v_readfirstlane_b32 s0, v0
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; GCN-NEXT: v_readfirstlane_b32 s1, v1
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 0)
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ret void
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}
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define amdgpu_ps void @prefetch_data_vgpr_base_vgpr_len(ptr addrspace(4) %ptr, i32 %len) {
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; SDAG-LABEL: prefetch_data_vgpr_base_vgpr_len:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: v_readfirstlane_b32 s2, v2
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; SDAG-NEXT: v_readfirstlane_b32 s0, v0
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; SDAG-NEXT: v_readfirstlane_b32 s1, v1
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; SDAG-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
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; SDAG-NEXT: s_endpgm
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;
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; GISEL-LABEL: prefetch_data_vgpr_base_vgpr_len:
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; GISEL: ; %bb.0: ; %entry
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; GISEL-NEXT: v_readfirstlane_b32 s0, v0
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; GISEL-NEXT: v_readfirstlane_b32 s1, v1
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; GISEL-NEXT: v_readfirstlane_b32 s2, v2
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; GISEL-NEXT: s_prefetch_data s[0:1], 0x0, s2, 0
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; GISEL-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
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ret void
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}
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define amdgpu_ps float @prefetch_and_load_b32(ptr addrspace(4) align 4 inreg %p) {
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; GCN-LABEL: prefetch_and_load_b32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_prefetch_data s[0:1], 0x0, null, 0
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; GCN-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ; return to shader part epilog
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entry:
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tail call void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %p, i32 0)
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%ret = load float, ptr addrspace(4) %p, align 4
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ret float %ret
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}
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declare void @llvm.amdgcn.s.prefetch.data.p4(ptr addrspace(4) %ptr, i32 %len)
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declare void @llvm.amdgcn.s.prefetch.data.p1(ptr addrspace(1) %ptr, i32 %len)
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declare void @llvm.amdgcn.s.prefetch.data.p0(ptr %ptr, i32 %len)
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