derek.holloway
7502bf64a4
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136 lines
6.3 KiB
YAML
136 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefix=RV32I
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# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
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# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB
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---
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name: bswap_i16
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body: |
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bb.0:
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liveins: $x10
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; RV32I-LABEL: name: bswap_i16
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASSERT_ZEXT]], [[C]](s32)
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; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]
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; RV32I-NEXT: $x10 = COPY [[AND]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i16
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; RV32ZBB_OR_RV32ZBKB: liveins: $x10
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; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)
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; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)
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; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = G_ASSERT_ZEXT %0, 16
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%2:_(s16) = G_TRUNC %1(s32)
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%3:_(s16) = G_BSWAP %2
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%4:_(s32) = G_ZEXT %3(s16)
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$x10 = COPY %4(s32)
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PseudoRET implicit $x10
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...
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---
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name: bswap_i32
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body: |
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bb.0:
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liveins: $x10
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; RV32I-LABEL: name: bswap_i32
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; RV32I: liveins: $x10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i32
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; RV32ZBB_OR_RV32ZBKB: liveins: $x10
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; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
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; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10
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%0:_(s32) = COPY $x10
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%1:_(s32) = G_BSWAP %0
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$x10 = COPY %1(s32)
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PseudoRET implicit $x10
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...
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---
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name: bswap_i64
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-LABEL: name: bswap_i64
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)
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; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
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; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]
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; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280
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; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)
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; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
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; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
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; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]
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; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]
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; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]
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; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; RV32I-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)
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; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]
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; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
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; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]
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; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]
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; RV32I-NEXT: $x10 = COPY [[OR2]](s32)
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; RV32I-NEXT: $x11 = COPY [[OR5]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
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;
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; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64
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; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11
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; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]
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; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]
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; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)
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; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)
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; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s64) = G_BSWAP %2
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%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
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$x10 = COPY %4(s32)
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$x11 = COPY %5(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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