TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/bitcast-cmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck %s

define { i1, <32 x i8> } @bitcast_v32i8(ptr %a0) {
; CHECK-LABEL: bitcast_v32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a1, 32
; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT:    vle8.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %src256 = load i256, ptr %a0, align 32
  %src256.bitcast = bitcast i256 %src256 to <32 x i8>
  %iszero = icmp eq i256 %src256, 0

  %res1 = insertvalue { i1, <32 x i8> } poison, i1 %iszero, 0
  %res2 = insertvalue { i1, <32 x i8> } %res1, <32 x i8> %src256.bitcast, 1
  ret { i1, <32 x i8> } %res2
}

define { i1, <16 x i16> } @bitcast_v16i16(ptr %a0) {
; CHECK-LABEL: bitcast_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vle16.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %src256 = load i256, ptr %a0, align 32
  %src256.bitcast = bitcast i256 %src256 to <16 x i16>
  %iszero = icmp eq i256 %src256, 0

  %res1 = insertvalue { i1, <16 x i16> } poison, i1 %iszero, 0
  %res2 = insertvalue { i1, <16 x i16> } %res1, <16 x i16> %src256.bitcast, 1
  ret { i1, <16 x i16> } %res2
}

define { i1, <8 x i32> } @bitcast_v8i32(ptr %a0) {
; CHECK-LABEL: bitcast_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %src256 = load i256, ptr %a0, align 32
  %src256.bitcast = bitcast i256 %src256 to <8 x i32>
  %iszero = icmp eq i256 %src256, 0

  %res1 = insertvalue { i1, <8 x i32> } poison, i1 %iszero, 0
  %res2 = insertvalue { i1, <8 x i32> } %res1, <8 x i32> %src256.bitcast, 1
  ret { i1, <8 x i32> } %res2
}

define i1 @bitcast_from_v32i8(ptr %a0) {
; CHECK-LABEL: bitcast_from_v32i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a1, 32
; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT:    vle8.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %vec = load <32 x i8>, ptr %a0, align 32
  %int = bitcast <32 x i8> %vec to i256
  %iszero = icmp eq i256 %int, 0
  ret i1 %iszero
}

define i1 @bitcast_from_v16i16(ptr %a0) {
; CHECK-LABEL: bitcast_from_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vle16.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %vec = load <16 x i16>, ptr %a0, align 32
  %int = bitcast <16 x i16> %vec to i256
  %iszero = icmp eq i256 %int, 0
  ret i1 %iszero
}

define i1 @bitcast_from_v8i32(ptr %a0) {
; CHECK-LABEL: bitcast_from_v8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vle32.v v8, (a0)
; CHECK-NEXT:    vmsne.vi v10, v8, 0
; CHECK-NEXT:    vcpop.m a0, v10
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %vec = load <8 x i32>, ptr %a0, align 32
  %int = bitcast <8 x i32> %vec to i256
  %iszero = icmp eq i256 %int, 0
  ret i1 %iszero
}

; Compare a plain i256 against a bitcasted vector.
define i1 @cmp_plain_to_v16i16(ptr %a0, ptr %a1) {
; CHECK-LABEL: cmp_plain_to_v16i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vle16.v v8, (a0)
; CHECK-NEXT:    vle16.v v10, (a1)
; CHECK-NEXT:    vmsne.vv v12, v8, v10
; CHECK-NEXT:    vcpop.m a0, v12
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %x = load i256, ptr %a0, align 32
  %y_vec = load <16 x i16>, ptr %a1, align 32
  %y = bitcast <16 x i16> %y_vec to i256
  %cmp = icmp eq i256 %x, %y
  ret i1 %cmp
}

; Flipped operands to guarantee the Y-path is covered regardless of DAG sorting.
define i1 @cmp_v16i16_to_plain(ptr %a0, ptr %a1) {
; CHECK-LABEL: cmp_v16i16_to_plain:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT:    vle16.v v8, (a0)
; CHECK-NEXT:    vle16.v v10, (a1)
; CHECK-NEXT:    vmsne.vv v12, v8, v10
; CHECK-NEXT:    vcpop.m a0, v12
; CHECK-NEXT:    seqz a0, a0
; CHECK-NEXT:    ret
  %x_vec = load <16 x i16>, ptr %a0, align 32
  %x = bitcast <16 x i16> %x_vec to i256
  %y = load i256, ptr %a1, align 32
  %cmp = icmp eq i256 %x, %y
  ret i1 %cmp
}