derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
64d7f43c751a4e2cdcbadd467aaf47daf2c7a244
TheRock/compiler/amd-llvm/llvm/test/Transforms/LoopInterchange/pr45743-move-from-inner-preheader.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

167 lines
7.0 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=loop-interchange -cache-line-size=64 -S %s | FileCheck %s
@global = external local_unnamed_addr global [400 x [400 x i32]], align 16
; We need to move %add from the inner loop pre header to the outer loop header
; before interchanging.
;
; outer_red = 0;
; for (i = 0; i < 391; i++) {
; add = i + 9;
; inner_red = outer_red;
; for (j = 0; j < 400; j++) {
; global[j][add] = 0;
; inner_red |= 20;
; }
; outer_red = inner_red;
; }
;
define void @test1() local_unnamed_addr #0 {
; CHECK-LABEL: define void @test1() local_unnamed_addr {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: br label %[[INNER_PH:.*]]
; CHECK: [[OUTER_HEADER_PREHEADER:.*]]:
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[OUTER_HEADER_PREHEADER]] ]
; CHECK-NEXT: [[INNER_RED:%.*]] = phi i32 [ [[OUTER_RED:%.*]], %[[OUTER_HEADER_PREHEADER]] ], [ [[RED_NEXT:%.*]], %[[OUTER_LATCH]] ]
; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[OUTER_IV]], 9
; CHECK-NEXT: br label %[[INNER_SPLIT1:.*]]
; CHECK: [[INNER_PH]]:
; CHECK-NEXT: br label %[[INNER:.*]]
; CHECK: [[INNER]]:
; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, %[[INNER_PH]] ], [ [[TMP0:%.*]], %[[INNER_SPLIT:.*]] ]
; CHECK-NEXT: [[OUTER_RED]] = phi i32 [ [[RED_NEXT_LCSSA:%.*]], %[[INNER_SPLIT]] ], [ 0, %[[INNER_PH]] ]
; CHECK-NEXT: br label %[[OUTER_HEADER_PREHEADER]]
; CHECK: [[INNER_SPLIT1]]:
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[TMP4]]
; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4
; CHECK-NEXT: [[RED_NEXT]] = or i32 [[INNER_RED]], 20
; CHECK-NEXT: [[INNER_IV_NEXT:%.*]] = add nsw i64 [[INNER_IV]], 1
; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 400
; CHECK-NEXT: br label %[[OUTER_LATCH]]
; CHECK: [[INNER_SPLIT]]:
; CHECK-NEXT: [[RED_NEXT_LCSSA]] = phi i32 [ [[RED_NEXT]], %[[OUTER_LATCH]] ]
; CHECK-NEXT: [[TMP0]] = add nsw i64 [[INNER_IV]], 1
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[TMP0]], 400
; CHECK-NEXT: br i1 [[TMP1]], label %[[EXIT:.*]], label %[[INNER]]
; CHECK: [[OUTER_LATCH]]:
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], 391
; CHECK-NEXT: br i1 [[EC_2]], label %[[INNER_SPLIT]], label %[[OUTER_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
bb:
br label %outer.header
outer.header: ; preds = %bb11, %bb
%outer.iv = phi i64 [ 0, %bb ], [ %outer.iv.next, %outer.latch ]
%outer.red = phi i32 [ 0, %bb ], [ %red.next.lcssa, %outer.latch ]
br label %inner.ph
inner.ph: ; preds = %bb1
%add = add nsw i64 %outer.iv, 9
br label %inner
inner: ; preds = %bb5, %bb3
%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
%ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %add
store i32 0, ptr %ptr
%red.next = or i32 %inner.red, 20
%inner.iv.next = add nsw i64 %inner.iv, 1
%ec.1 = icmp eq i64 %inner.iv.next, 400
br i1 %ec.1, label %outer.latch, label %inner
outer.latch: ; preds = %bb5
%red.next.lcssa = phi i32 [ %red.next, %inner ]
%outer.iv.next = add nsw i64 %outer.iv, 1
%ec.2 = icmp eq i64 %outer.iv.next, 391
br i1 %ec.2, label %exit, label %outer.header
exit: ; preds = %bb11
ret void
}
declare void @side_effect()
; Cannot interchange, as the inner loop preheader contains a call to a function
; with side effects.
;
; outer_red = 0;
; for (i = 0; i < 391; i++) {
; add = i + 9;
; side_effect();
; inner_red = outer_red;
; for (j = 0; j < 400; j++) {
; global[j][add] = 0;
; inner_red |= 20;
; }
; outer_red = inner_red;
; }
;
define void @test2() {
; CHECK-LABEL: define void @test2() {
; CHECK-NEXT: [[BB:.*]]:
; CHECK-NEXT: br label %[[OUTER_HEADER:.*]]
; CHECK: [[OUTER_HEADER]]:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, %[[BB]] ], [ [[OUTER_IV_NEXT:%.*]], %[[OUTER_LATCH:.*]] ]
; CHECK-NEXT: [[OUTER_RED:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[RED_NEXT_LCSSA:%.*]], %[[OUTER_LATCH]] ]
; CHECK-NEXT: br label %[[INNER_PH:.*]]
; CHECK: [[INNER_PH]]:
; CHECK-NEXT: [[TMP4:%.*]] = add nsw i64 [[OUTER_IV]], 9
; CHECK-NEXT: call void @side_effect()
; CHECK-NEXT: br label %[[INNER:.*]]
; CHECK: [[INNER]]:
; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, %[[INNER_PH]] ], [ [[INNER_IV_NEXT:%.*]], %[[INNER]] ]
; CHECK-NEXT: [[INNER_RED:%.*]] = phi i32 [ [[OUTER_RED]], %[[INNER_PH]] ], [ [[RED_NEXT:%.*]], %[[INNER]] ]
; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 [[INNER_IV]], i64 [[TMP4]]
; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4
; CHECK-NEXT: [[RED_NEXT]] = or i32 [[INNER_RED]], 20
; CHECK-NEXT: [[INNER_IV_NEXT]] = add nsw i64 [[INNER_IV]], 1
; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i64 [[INNER_IV_NEXT]], 400
; CHECK-NEXT: br i1 [[EC_1]], label %[[OUTER_LATCH]], label %[[INNER]]
; CHECK: [[OUTER_LATCH]]:
; CHECK-NEXT: [[RED_NEXT_LCSSA]] = phi i32 [ [[RED_NEXT]], %[[INNER]] ]
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add nsw i64 [[OUTER_IV]], 1
; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i64 [[OUTER_IV_NEXT]], 391
; CHECK-NEXT: br i1 [[EC_2]], label %[[EXIT:.*]], label %[[OUTER_HEADER]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
bb:
br label %outer.header
outer.header: ; preds = %bb11, %bb
%outer.iv = phi i64 [ 0, %bb ], [ %outer.iv.next, %outer.latch ]
%outer.red = phi i32 [ 0, %bb ], [ %red.next.lcssa, %outer.latch ]
br label %inner.ph
inner.ph: ; preds = %bb1
%add = add nsw i64 %outer.iv, 9
call void @side_effect()
br label %inner
inner: ; preds = %bb5, %bb3
%inner.iv = phi i64 [ 0, %inner.ph ], [ %inner.iv.next, %inner ]
%inner.red = phi i32 [ %outer.red, %inner.ph ], [ %red.next, %inner ]
%ptr = getelementptr inbounds [400 x [400 x i32]], ptr @global, i64 0, i64 %inner.iv, i64 %add
store i32 0, ptr %ptr
%red.next = or i32 %inner.red, 20
%inner.iv.next = add nsw i64 %inner.iv, 1
%ec.1 = icmp eq i64 %inner.iv.next, 400
br i1 %ec.1, label %outer.latch, label %inner
outer.latch: ; preds = %bb5
%red.next.lcssa = phi i32 [ %red.next, %inner ]
%outer.iv.next = add nsw i64 %outer.iv, 1
%ec.2 = icmp eq i64 %outer.iv.next, 391
br i1 %ec.2, label %exit, label %outer.header
exit: ; preds = %bb11
ret void
}
Reference in new issue View Git Blame Copy Permalink