derek.holloway
7502bf64a4
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80 lines
4.8 KiB
ArmAsm
80 lines
4.8 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -mattr='+xsfvfnrclipxfqf' -iterations=1 -instruction-tables=full %s | \
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# RUN: FileCheck %s
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vsetvli a0, zero, e8, mf8, ta, ma
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sf.vfnrclip.xu.f.qf v4, v8, fa2
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vsetvli a0, zero, e8, mf4, ta, ma
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sf.vfnrclip.xu.f.qf v4, v8, fa2
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vsetvli a0, zero, e8, mf2, ta, ma
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sf.vfnrclip.xu.f.qf v4, v8, fa2
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vsetvli a0, zero, e8, m1, ta, ma
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sf.vfnrclip.xu.f.qf v4, v8, fa2
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vsetvli a0, zero, e8, m2, ta, ma
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sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1
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# CHECK-NEXT: [5] - VLEN512SiFive7VA1:1
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# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1
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# CHECK-NEXT: [7] - VLEN512SiFive7VL:1
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# CHECK-NEXT: [8] - VLEN512SiFive7VS:1
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK-NEXT: [7]: Bypass Latency
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# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
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# CHECK-NEXT: [9]: LLVM Opcode Name
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# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf8, ta, ma
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# CHECK-NEXT: 1 7 1.00 7 VLEN512SiFive7VA1[1,2],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf4, ta, ma
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# CHECK-NEXT: 1 8 2.00 8 VLEN512SiFive7VA1[1,3],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, mf2, ta, ma
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# CHECK-NEXT: 1 10 4.00 10 VLEN512SiFive7VA1[1,5],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m1, ta, ma
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# CHECK-NEXT: 1 13 8.00 13 VLEN512SiFive7VA1[1,9],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli a0, zero, e8, m2, ta, ma
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# CHECK-NEXT: 1 19 16.00 19 VLEN512SiFive7VA1[1,17],VLEN512SiFive7VCQ SF_VFNRCLIP_XU_F_QF sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK: Resources:
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# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
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# CHECK-NEXT: [1] - VLEN512SiFive7IDiv
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# CHECK-NEXT: [2] - VLEN512SiFive7PipeA
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# CHECK-NEXT: [3] - VLEN512SiFive7PipeB
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# CHECK-NEXT: [4] - VLEN512SiFive7VA1
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# CHECK-NEXT: [5] - VLEN512SiFive7VCQ
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# CHECK-NEXT: [6] - VLEN512SiFive7VL
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# CHECK-NEXT: [7] - VLEN512SiFive7VS
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
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# CHECK-NEXT: - - 5.00 - 36.00 5.00 - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf8, ta, ma
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# CHECK-NEXT: - - - - 2.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf4, ta, ma
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# CHECK-NEXT: - - - - 3.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, mf2, ta, ma
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# CHECK-NEXT: - - - - 5.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, m1, ta, ma
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# CHECK-NEXT: - - - - 9.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa2
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# CHECK-NEXT: - - 1.00 - - - - - vsetvli a0, zero, e8, m2, ta, ma
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# CHECK-NEXT: - - - - 17.00 1.00 - - sf.vfnrclip.xu.f.qf v4, v8, fa2
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