derek.holloway
7502bf64a4
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313 lines
14 KiB
C++
313 lines
14 KiB
C++
#include "../util/StringUtility.h"
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//#include "sage3basic.h"
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#include "BaseSemantics2.h"
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//#include "Diagnostics.h"
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#include "DispatcherAMDGPU.h"
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#include "../integerOps.h"
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#include "SymEvalSemantics.h"
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#include "../SgAsmExpression.h"
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#include "../conversions.h"
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#undef si_value // name pollution from siginfo.h
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namespace rose {
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namespace BinaryAnalysis {
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namespace InstructionSemantics2 {
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/*******************************************************************************************************************************
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* Support functions
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*******************************************************************************************************************************/
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static inline size_t asm_type_width(SgAsmType *ty) {
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ASSERT_not_null(ty);
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return ty->get_nBits();
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}
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/*******************************************************************************************************************************
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* Base AMDGPU instruction processor
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*******************************************************************************************************************************/
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namespace AMDGPU {
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void
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InsnProcessor::process(const BaseSemantics::DispatcherPtr &dispatcher_, SgAsmInstruction *insn_) {
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DispatcherAMDGPUPtr dispatcher = DispatcherAMDGPU::promote(dispatcher_);
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BaseSemantics::RiscOperatorsPtr operators = dispatcher->get_operators();
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SgAsmAMDGPUInstruction *insn = isSgAsmAMDGPUInstruction(insn_);
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ASSERT_require(insn != NULL && insn == operators->currentInstruction());
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dispatcher->advanceInstructionPointer(insn);
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SgAsmExpressionPtrList &operands = insn->get_operandList()->get_operands();
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//check_arg_width(dispatcher.get(), insn, operands);
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uint32_t raw = 0;
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std::vector<unsigned char> rawBytes = insn->get_raw_bytes();
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for (int idx = 0; idx < rawBytes.size(); idx++) {
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raw |= (rawBytes[idx] << (8 * idx));
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}
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p(dispatcher.get(), operators.get(), insn, operands, raw);
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}
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void
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InsnProcessor::assert_args(I insn, A args, size_t nargs) {
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if (args.size() != nargs) {
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std::string mesg = "instruction has incorrect number of args";
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throw BaseSemantics::Exception(mesg, insn);
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}
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}
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/*******************************************************************************************************************************
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* Functors that handle individual AMDGPU instructions kinds
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*******************************************************************************************************************************/
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typedef InsnProcessor P;
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struct IP_s_add_u32 : P {
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void p(D d, Ops ops, I insn, A args, B raw) {
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BaseSemantics::SValuePtr src1;
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BaseSemantics::SValuePtr src0;
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if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){
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src1 = ops->number_(64, ival->get_value());
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}else{
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src1 = ops->unsignedExtend(d->read(args[1]),64);
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}
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if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){
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src0 = ops->number_(64, ival->get_value());
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}else{
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src0 = ops->unsignedExtend(d->read(args[2]),64);
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}
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BaseSemantics::SValuePtr result;
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BaseSemantics::SValuePtr n, z, c, v;
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result = d->doAddOperation( src0 , src1 ,false,ops->boolean_(false),n,z,c,v);
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BaseSemantics::SValuePtr scc_value;
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scc_value = ops->ite(
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ops->isUnsignedGreaterThanOrEqual(result,ops->number_(64,0x100000000)),
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ops->number_(1,1),
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ops->number_(1,0));
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d->writeRegister(d->REG_SCC,scc_value);
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d->write(args[0],ops->extract(result,0,32));
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//d->writeRegister(d->REG_SCC,c);
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}
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};
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struct IP_s_addc_u32 : P {
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void p(D d, Ops ops, I insn, A args, B raw) {
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BaseSemantics::SValuePtr src1;
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BaseSemantics::SValuePtr src0;
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if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[1])){
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src1 = ops->number_(64, ival->get_value());
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}else{
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src1 = ops->unsignedExtend(d->read(args[1]),64);
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}
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if(SgAsmIntegerValueExpression * ival = isSgAsmIntegerValueExpression(args[2])){
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src0 = ops->number_(64, ival->get_value());
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}else{
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src0 = ops->unsignedExtend(d->read(args[2]),64);
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}
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BaseSemantics::SValuePtr result;
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BaseSemantics::SValuePtr n, z, c, v;
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BaseSemantics::SValuePtr old_scc = d->readRegister(d->REG_SCC);
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result = d->doAddOperation( src0 , src1 ,false,
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d->readRegister(d->REG_SCC)
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,n,z,c,v);
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d->write(args[0],ops->extract(result,0,32));
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d->writeRegister(d->REG_SCC,c);
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}
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};
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struct IP_s_getpc_b64 : P {
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void p(D d, Ops ops, I insn, A args, B raw) {
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SgAsmIntegerValueExpression *ival = isSgAsmIntegerValueExpression(args[2]);
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BaseSemantics::SValuePtr result = ops->number_(ival->get_significantBits(), ival->get_value());
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BaseSemantics::SValuePtr lowPC = ops->extract(result,0,32);
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BaseSemantics::SValuePtr highPC = ops->shiftRight(result,ops->number_(32,32));
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d->write(args[0],lowPC);
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d->write(args[1],highPC);
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}
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};
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struct IP_s_setpc_b64 : P {
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void p(D d, Ops ops, I insn, A args, B raw) {
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BaseSemantics::SValuePtr result;
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BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[0]),0,32);
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BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[1]),64);
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BaseSemantics::SValuePtr n, z, c, v;
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result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v);
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d->writeRegister(d->REG_PC, result);
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}
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};
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struct IP_s_swappc_b64 : P {
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void p(D d, Ops ops, I insn, A args, B raw) {
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BaseSemantics::SValuePtr result = d->readRegister(d->REG_PC);
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BaseSemantics::SValuePtr storelowPC = result;
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BaseSemantics::SValuePtr storehighPC = ops->shiftRight(result,ops->number_(32,32));
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d->write(args[0],storelowPC);
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d->write(args[1],storehighPC);
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BaseSemantics::SValuePtr n, z, c, v;
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BaseSemantics::SValuePtr lowPC = ops->extract(d->read(args[2]),0,32);
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BaseSemantics::SValuePtr highPC = d->ZeroExtend(d->read(args[3]),64);
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result = d->doAddOperation( ops->shiftLeft(highPC, ops->number_(32,32)) , lowPC,false,ops->boolean_(false),n,z,c,v);
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d->writeRegister(d->REG_PC, result);
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}
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};
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} // namespace
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/*******************************************************************************************************************************
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* DispatcherAMDGPU
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*******************************************************************************************************************************/
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void
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DispatcherAMDGPU::iproc_init() {
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iproc_set(rose_amdgpu_op_s_getpc_b64, new AMDGPU::IP_s_getpc_b64);
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iproc_set(rose_amdgpu_op_s_setpc_b64, new AMDGPU::IP_s_setpc_b64);
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iproc_set(rose_amdgpu_op_s_swappc_b64, new AMDGPU::IP_s_swappc_b64);
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iproc_set(rose_amdgpu_op_s_add_u32, new AMDGPU::IP_s_add_u32);
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iproc_set(rose_amdgpu_op_s_addc_u32, new AMDGPU::IP_s_addc_u32);
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}
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void
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DispatcherAMDGPU::regcache_init() {
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if (regdict) {
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REG_PC = findRegister("pc_all", 64);
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REG_SCC = findRegister("src_scc", 1);
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}
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}
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void
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DispatcherAMDGPU::memory_init() {
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if (BaseSemantics::StatePtr state = currentState()) {
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if (BaseSemantics::MemoryStatePtr memory = state->memoryState()) {
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switch (memory->get_byteOrder()) {
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case ByteOrder::ORDER_LSB:
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break;
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case ByteOrder::ORDER_MSB:
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break;
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case ByteOrder::ORDER_UNSPECIFIED:
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memory->set_byteOrder(ByteOrder::ORDER_LSB);
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break;
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}
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}
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}
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}
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RegisterDescriptor
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DispatcherAMDGPU::instructionPointerRegister() const {
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return REG_PC;
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}
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RegisterDescriptor
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DispatcherAMDGPU::stackPointerRegister() const {
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assert(0 && "not implemented");
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return REG_SCC;
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}
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void
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DispatcherAMDGPU::set_register_dictionary(const RegisterDictionary *regdict) {
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BaseSemantics::Dispatcher::set_register_dictionary(regdict);
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regcache_init();
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}
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void
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DispatcherAMDGPU::setFlagsForResult(const BaseSemantics::SValuePtr &result,
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const BaseSemantics::SValuePtr &carries,
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bool invertCarries, size_t nbits,
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BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z,
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BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) {
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size_t width = result->get_width();
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n = operators->extract(result, width - 1, width);
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z = operators->equalToZero(result);
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BaseSemantics::SValuePtr sign = operators->extract(carries, nbits - 1, nbits);
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BaseSemantics::SValuePtr ofbit = operators->extract(carries, nbits - 2, nbits - 1);
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c = invertMaybe(sign, invertCarries);
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v = operators->xor_(sign, ofbit);
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}
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BaseSemantics::SValuePtr
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DispatcherAMDGPU::invertMaybe(const BaseSemantics::SValuePtr &value, bool maybe) {
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return maybe ? operators->invert(value) : value;
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}
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BaseSemantics::SValuePtr
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DispatcherAMDGPU::SignExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) {
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ASSERT_require(newsize > 0);
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return operators->signExtend(expr, newsize);
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}
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BaseSemantics::SValuePtr
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DispatcherAMDGPU::ZeroExtend(const BaseSemantics::SValuePtr &expr, size_t newsize) {
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ASSERT_require(newsize > 0);
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return operators->unsignedExtend(expr, newsize);
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}
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BaseSemantics::SValuePtr
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DispatcherAMDGPU::doAddOperation(BaseSemantics::SValuePtr a, BaseSemantics::SValuePtr b,
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bool invertCarries, const BaseSemantics::SValuePtr &carryIn,
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BaseSemantics::SValuePtr &n, BaseSemantics::SValuePtr &z,
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BaseSemantics::SValuePtr &c, BaseSemantics::SValuePtr &v) {
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if (a->get_width() > b->get_width()) {
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b = operators->signExtend(b, a->get_width());
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} else if (a->get_width() < b->get_width()) {
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a = operators->signExtend(a, b->get_width());
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}
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ASSERT_require(1 == carryIn->get_width());
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size_t nbits = a->get_width();
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BaseSemantics::SValuePtr carries;
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BaseSemantics::SValuePtr result = operators->addWithCarries(a, b,
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invertMaybe(carryIn, invertCarries),
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carries/*out*/);
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setFlagsForResult(result, carries, invertCarries, a->get_width(), n, z, c, v);
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return result;
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}
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BaseSemantics::SValuePtr
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DispatcherAMDGPU::readRegister(const RegisterDescriptor ®) {
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return operators->readRegister(reg);
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}
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void
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DispatcherAMDGPU::writeRegister(const RegisterDescriptor ®, const BaseSemantics::SValuePtr &value) {
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operators->writeRegister(reg, value);
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}
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void
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DispatcherAMDGPU::write(SgAsmExpression *e, const BaseSemantics::SValuePtr &value,
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size_t addr_nbits/*=0*/) {
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if (SgAsmDirectRegisterExpression *re = isSgAsmDirectRegisterExpression(e)) {
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writeRegister(re->get_descriptor(), value);
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} else {
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Dispatcher::write(e, value, addr_nbits); // defer to super class
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}
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}
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} // namespace
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} // namespace
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} // namespace
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//using namespace rose::Diagnostics;
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