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125 lines
4.3 KiB
C++
125 lines
4.3 KiB
C++
//===- bolt/Passes/AArch64RelaxationPass.cpp ------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64RelaxationPass class.
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//
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//===----------------------------------------------------------------------===//
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#include "bolt/Passes/AArch64RelaxationPass.h"
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#include "bolt/Core/ParallelUtilities.h"
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#include "bolt/Utils/CommandLineOpts.h"
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#include <iterator>
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using namespace llvm;
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namespace opts {
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extern cl::OptionCategory BoltCategory;
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static cl::opt<bool> AArch64PassOpt(
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"aarch64-relaxation",
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cl::desc("Replace ARM non-local ADR/LDR instructions with ADRP"),
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cl::init(true), cl::cat(BoltCategory), cl::ReallyHidden);
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} // namespace opts
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namespace llvm {
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namespace bolt {
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// We don't exit directly from runOnFunction since it would call ThreadPool
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// destructor which might result in internal assert if we're not finished
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// creating async jobs on the moment of exit. So we're finishing all parallel
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// jobs and checking the exit flag after it.
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static bool PassFailed = false;
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void AArch64RelaxationPass::runOnFunction(BinaryFunction &BF) {
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if (PassFailed)
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return;
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BinaryContext &BC = BF.getBinaryContext();
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for (BinaryBasicBlock &BB : BF) {
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for (auto It = BB.begin(); It != BB.end(); ++It) {
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MCInst &Inst = *It;
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bool IsADR = BC.MIB->isADR(Inst);
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// TODO: Handle other types of LDR (literal, PC-relative) instructions.
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if (!IsADR && !BC.MIB->isLoadLiteralGPR(Inst))
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continue;
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const MCSymbol *Symbol = BC.MIB->getTargetSymbol(Inst, IsADR ? 0 : 1);
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if (!Symbol)
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continue;
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if (BF.hasIslandsInfo()) {
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BinaryFunction::IslandInfo &Islands = BF.getIslandInfo();
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if (Islands.Symbols.count(Symbol) || Islands.ProxySymbols.count(Symbol))
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continue;
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}
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// Don't relax ADR/LDR if it points to the same function and is in the
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// main fragment and BF initial size is < 1MB.
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const unsigned OneMB = 0x100000;
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if (BF.getSize() < OneMB) {
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BinaryFunction *TargetBF = BC.getFunctionForSymbol(Symbol);
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if (TargetBF == &BF && !BB.isSplit())
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continue;
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// No relaxation needed if ADR/LDR references a basic block in the same
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// fragment.
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if (BinaryBasicBlock *TargetBB = BF.getBasicBlockForLabel(Symbol))
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if (BB.getFragmentNum() == TargetBB->getFragmentNum())
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continue;
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}
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InstructionListType AdrpMaterialization;
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{
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auto L = BC.scopeLock();
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AdrpMaterialization =
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IsADR ? BC.MIB->undoAdrpAddRelaxation(Inst, BC.Ctx.get())
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: BC.MIB->createAdrpLdr(Inst, BC.Ctx.get());
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}
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if (It != BB.begin() && BC.MIB->isNoop(*std::prev(It))) {
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It = BB.eraseInstruction(std::prev(It));
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} else if (std::next(It) != BB.end() && BC.MIB->isNoop(*std::next(It))) {
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BB.eraseInstruction(std::next(It));
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} else if (!BF.isSimple()) {
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// If the function is not simple, it may contain a jump table undetected
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// by us. This jump table may use an offset from the branch instruction
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// to land in the desired place. If we add new instructions, we
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// invalidate this offset, so we have to rely on linker-inserted NOP to
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// replace it with ADRP, and abort if it is not present.
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auto L = BC.scopeLock();
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BC.errs() << "BOLT-ERROR: cannot relax " << (IsADR ? "ADR" : "LDR")
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<< " in non-simple function " << BF << '\n';
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PassFailed = true;
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return;
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}
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It = BB.replaceInstruction(It, AdrpMaterialization);
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}
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}
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}
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Error AArch64RelaxationPass::runOnFunctions(BinaryContext &BC) {
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if (!opts::AArch64PassOpt || !BC.HasRelocations)
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return Error::success();
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ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) {
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runOnFunction(BF);
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};
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ParallelUtilities::runOnEachFunction(
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BC, ParallelUtilities::SchedulingPolicy::SP_TRIVIAL, WorkFun, nullptr,
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"AArch64RelaxationPass");
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if (PassFailed)
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return createFatalBOLTError("");
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return Error::success();
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}
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} // end namespace bolt
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} // end namespace llvm
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