derek.holloway
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482 lines
20 KiB
TableGen
482 lines
20 KiB
TableGen
//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'A', Atomic
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// Instructions extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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def ordering : RISCVOp {
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let OperandType = "OPERAND_ATOMIC_ORDERING";
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}
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
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}
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multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : LR_r<0, 0, funct3, opcodestr>;
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def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQRL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class SC_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00011, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs2, $rs1">;
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multiclass SC_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : SC_r<0, 0, funct3, opcodestr>;
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def _AQ : SC_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : SC_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQRL : SC_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs2, $rs1">;
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multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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def _AQRL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1 in {
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defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
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defm SC_W : SC_r_aq_rl<0b010, "sc.w">,
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Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
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} // Predicates = [HasStdExtZalrsc], IsSignExtendingOpW = 1
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let Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1 in {
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defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">,
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Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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} // Predicates = [HasStdExtZaamo], IsSignExtendingOpW = 1
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let Predicates = [HasStdExtZalrsc, IsRV64] in {
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defm LR_D : LR_r_aq_rl<0b011, "lr.d">, Sched<[WriteAtomicLDD, ReadAtomicLDD]>;
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defm SC_D : SC_r_aq_rl<0b011, "sc.d">,
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Sched<[WriteAtomicSTD, ReadAtomicSTD, ReadAtomicSTD]>;
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} // Predicates = [HasStdExtZalrsc, IsRV64]
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let Predicates = [HasStdExtZaamo, IsRV64] in {
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defm AMOSWAP_D : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOADD_D : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOXOR_D : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOAND_D : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOOR_D : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMIN_D : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAX_D : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMINU_D : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
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Sched<[WriteAtomicD, ReadAtomicDA, ReadAtomicDD]>;
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} // Predicates = [HasStdExtZaamo, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let IsAtomic = 1 in {
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// An atomic load operation that does not need either acquire or release
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// semantics.
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class relaxed_load<PatFrags base>
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: PatFrag<(ops node:$ptr), (base node:$ptr)> {
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let IsAtomicOrderingAcquireOrStronger = 0;
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}
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// A atomic load operation that actually needs acquire semantics.
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class acquiring_load<PatFrags base>
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: PatFrag<(ops node:$ptr), (base node:$ptr)> {
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let IsAtomicOrderingAcquire = 1;
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}
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// An atomic load operation that needs sequential consistency.
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class seq_cst_load<PatFrags base>
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: PatFrag<(ops node:$ptr), (base node:$ptr)> {
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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// An atomic store operation that does not need either acquire or release
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// semantics.
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class relaxed_store<PatFrag base>
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: PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
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let IsAtomicOrderingReleaseOrStronger = 0;
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}
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// A store operation that actually needs release semantics.
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class releasing_store<PatFrag base>
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: PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
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let IsAtomicOrderingRelease = 1;
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}
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// A store operation that actually needs sequential consistency.
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class seq_cst_store<PatFrag base>
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: PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr)> {
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let IsAtomicOrderingSequentiallyConsistent = 1;
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}
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} // IsAtomic = 1
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// Atomic load/store are available under +zalrsc (thus also +a) and
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// +force-atomics. Fences will be inserted for atomic load/stores according to
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// the logic in RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
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// The normal loads/stores are relaxed (unordered) loads/stores that don't have
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// any ordering. This is necessary because AtomicExpandPass has added fences to
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// atomic load/stores and changed them to unordered ones.
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let Predicates = [HasAtomicLdSt] in {
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// Use unsigned for aext due to no c.lb in Zcb.
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def : LdPat<relaxed_load<atomic_load_sext_8>, LB>;
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def : LdPat<relaxed_load<atomic_load_azext_8>, LBU>;
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def : LdPat<relaxed_load<atomic_load_asext_16>, LH>;
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def : LdPat<relaxed_load<atomic_load_zext_16>, LHU>;
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def : StPat<relaxed_store<atomic_store_8>, SB, GPR, XLenVT>;
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def : StPat<relaxed_store<atomic_store_16>, SH, GPR, XLenVT>;
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def : StPat<relaxed_store<atomic_store_32>, SW, GPR, XLenVT>;
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}
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let Predicates = [HasAtomicLdSt, IsRV32] in {
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def : LdPat<relaxed_load<atomic_load_nonext_32>, LW, i32>;
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}
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let Predicates = [HasAtomicLdSt, IsRV64] in {
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def : LdPat<relaxed_load<atomic_load_asext_32>, LW, i64>;
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def : LdPat<relaxed_load<atomic_load_zext_32>, LWU, i64>;
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def : LdPat<relaxed_load<atomic_load_nonext_64>, LD, i64>;
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def : StPat<relaxed_store<atomic_store_64>, SD, GPR, i64>;
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}
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/// AMOs
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class PatAMO<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
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: Pat<(vt (OpNode (XLenVT GPR:$rs1), (vt GPR:$rs2))), (Inst GPR:$rs2, GPR:$rs1)>;
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multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT,
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list<Predicate> ExtraPreds = []> {
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let Predicates = !listconcat([HasStdExtA, NoStdExtZtso], ExtraPreds) in {
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_monotonic"),
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!cast<RVInst>(BaseInst), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_acquire"),
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!cast<RVInst>(BaseInst#"_AQ"), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_release"),
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!cast<RVInst>(BaseInst#"_RL"), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_acq_rel"),
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!cast<RVInst>(BaseInst#"_AQRL"), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_seq_cst"),
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!cast<RVInst>(BaseInst#"_AQRL"), vt>;
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}
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let Predicates = !listconcat([HasStdExtA, HasStdExtZtso], ExtraPreds) in {
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_monotonic"),
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!cast<RVInst>(BaseInst), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_acquire"),
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!cast<RVInst>(BaseInst), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_release"),
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!cast<RVInst>(BaseInst), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_acq_rel"),
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!cast<RVInst>(BaseInst), vt>;
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def : PatAMO<!cast<PatFrag>(AtomicOp#"_seq_cst"),
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!cast<RVInst>(BaseInst), vt>;
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}
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}
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defm : AMOPat<"atomic_swap_i32", "AMOSWAP_W">;
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defm : AMOPat<"atomic_load_add_i32", "AMOADD_W">;
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defm : AMOPat<"atomic_load_and_i32", "AMOAND_W">;
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defm : AMOPat<"atomic_load_or_i32", "AMOOR_W">;
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defm : AMOPat<"atomic_load_xor_i32", "AMOXOR_W">;
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defm : AMOPat<"atomic_load_max_i32", "AMOMAX_W">;
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defm : AMOPat<"atomic_load_min_i32", "AMOMIN_W">;
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defm : AMOPat<"atomic_load_umax_i32", "AMOMAXU_W">;
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defm : AMOPat<"atomic_load_umin_i32", "AMOMINU_W">;
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defm : AMOPat<"atomic_swap_i64", "AMOSWAP_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_add_i64", "AMOADD_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_and_i64", "AMOAND_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_or_i64", "AMOOR_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_xor_i64", "AMOXOR_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_max_i64", "AMOMAX_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_min_i64", "AMOMIN_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_umax_i64", "AMOMAXU_D", i64, [IsRV64]>;
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defm : AMOPat<"atomic_load_umin_i64", "AMOMINU_D", i64, [IsRV64]>;
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/// Pseudo AMOs
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class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMO
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: Pseudo<(outs GPR:$res, GPR:$scratch),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMOMinMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, GPR:$sextshamt,
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ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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class PseudoMaskedAMOUMinUMax
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: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
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(ins GPR:$addr, GPR:$incr, GPR:$mask, ordering:$ordering), []> {
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let Constraints = "@earlyclobber $res,@earlyclobber $scratch1,"
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"@earlyclobber $scratch2";
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let mayLoad = 1;
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let mayStore = 1;
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let hasSideEffects = 0;
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}
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// Ordering constants must be kept in sync with the AtomicOrdering enum in
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// AtomicOrdering.h.
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multiclass PseudoAMOPat<string AtomicOp, Pseudo AMOInst, ValueType vt = XLenVT> {
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def : Pat<(vt (!cast<PatFrag>(AtomicOp#"_monotonic") GPR:$addr, GPR:$incr)),
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(AMOInst GPR:$addr, GPR:$incr, 2)>;
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def : Pat<(vt (!cast<PatFrag>(AtomicOp#"_acquire") GPR:$addr, GPR:$incr)),
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(AMOInst GPR:$addr, GPR:$incr, 4)>;
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def : Pat<(vt (!cast<PatFrag>(AtomicOp#"_release") GPR:$addr, GPR:$incr)),
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(AMOInst GPR:$addr, GPR:$incr, 5)>;
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def : Pat<(vt (!cast<PatFrag>(AtomicOp#"_acq_rel") GPR:$addr, GPR:$incr)),
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(AMOInst GPR:$addr, GPR:$incr, 6)>;
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def : Pat<(vt (!cast<PatFrag>(AtomicOp#"_seq_cst") GPR:$addr, GPR:$incr)),
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(AMOInst GPR:$addr, GPR:$incr, 7)>;
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}
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class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(XLenVT (intrin (XLenVT GPR:$addr), (XLenVT GPR:$incr),
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(XLenVT GPR:$mask), (XLenVT timm:$ordering))),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering)>;
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class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(XLenVT (intrin (XLenVT GPR:$addr), (XLenVT GPR:$incr),
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(XLenVT GPR:$mask), (XLenVT GPR:$shiftamt),
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(XLenVT timm:$ordering))),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
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timm:$ordering)>;
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let Predicates = [HasStdExtZalrsc, NoStdExtZaamo] in {
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|
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let Size = 16 in {
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def PseudoAtomicSwap32 : PseudoAMO;
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def PseudoAtomicLoadAdd32 : PseudoAMO;
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def PseudoAtomicLoadSub32 : PseudoAMO;
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def PseudoAtomicLoadAnd32 : PseudoAMO;
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def PseudoAtomicLoadOr32 : PseudoAMO;
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def PseudoAtomicLoadXor32 : PseudoAMO;
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} // Size = 16
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let Size = 24 in {
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def PseudoAtomicLoadMax32 : PseudoAMO;
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def PseudoAtomicLoadMin32 : PseudoAMO;
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def PseudoAtomicLoadUMax32 : PseudoAMO;
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def PseudoAtomicLoadUMin32 : PseudoAMO;
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} // Size = 24
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defm : PseudoAMOPat<"atomic_swap_i32", PseudoAtomicSwap32>;
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defm : PseudoAMOPat<"atomic_load_add_i32", PseudoAtomicLoadAdd32>;
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defm : PseudoAMOPat<"atomic_load_sub_i32", PseudoAtomicLoadSub32>;
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defm : PseudoAMOPat<"atomic_load_and_i32", PseudoAtomicLoadAnd32>;
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defm : PseudoAMOPat<"atomic_load_or_i32", PseudoAtomicLoadOr32>;
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defm : PseudoAMOPat<"atomic_load_xor_i32", PseudoAtomicLoadXor32>;
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defm : PseudoAMOPat<"atomic_load_max_i32", PseudoAtomicLoadMax32>;
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defm : PseudoAMOPat<"atomic_load_min_i32", PseudoAtomicLoadMin32>;
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defm : PseudoAMOPat<"atomic_load_umax_i32", PseudoAtomicLoadUMax32>;
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defm : PseudoAMOPat<"atomic_load_umin_i32", PseudoAtomicLoadUMin32>;
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} // Predicates = [HasStdExtZalrsc, NoStdExtZaamo]
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|
|
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let Predicates = [HasStdExtZalrsc, NoStdExtZaamo, IsRV64] in {
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|
|
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let Size = 16 in {
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def PseudoAtomicSwap64 : PseudoAMO;
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def PseudoAtomicLoadAdd64 : PseudoAMO;
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def PseudoAtomicLoadSub64 : PseudoAMO;
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def PseudoAtomicLoadAnd64 : PseudoAMO;
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def PseudoAtomicLoadOr64 : PseudoAMO;
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def PseudoAtomicLoadXor64 : PseudoAMO;
|
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} // Size = 16
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|
let Size = 24 in {
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|
def PseudoAtomicLoadMax64 : PseudoAMO;
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def PseudoAtomicLoadMin64 : PseudoAMO;
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def PseudoAtomicLoadUMax64 : PseudoAMO;
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def PseudoAtomicLoadUMin64 : PseudoAMO;
|
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} // Size = 24
|
|
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defm : PseudoAMOPat<"atomic_swap_i64", PseudoAtomicSwap64, i64>;
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defm : PseudoAMOPat<"atomic_load_add_i64", PseudoAtomicLoadAdd64, i64>;
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defm : PseudoAMOPat<"atomic_load_sub_i64", PseudoAtomicLoadSub64, i64>;
|
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defm : PseudoAMOPat<"atomic_load_and_i64", PseudoAtomicLoadAnd64, i64>;
|
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defm : PseudoAMOPat<"atomic_load_or_i64", PseudoAtomicLoadOr64, i64>;
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defm : PseudoAMOPat<"atomic_load_xor_i64", PseudoAtomicLoadXor64, i64>;
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defm : PseudoAMOPat<"atomic_load_max_i64", PseudoAtomicLoadMax64, i64>;
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defm : PseudoAMOPat<"atomic_load_min_i64", PseudoAtomicLoadMin64, i64>;
|
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defm : PseudoAMOPat<"atomic_load_umax_i64", PseudoAtomicLoadUMax64, i64>;
|
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defm : PseudoAMOPat<"atomic_load_umin_i64", PseudoAtomicLoadUMin64, i64>;
|
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} // Predicates = [HasStdExtZalrsc, NoStdExtZaamo, IsRV64]
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|
|
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let Predicates = [HasStdExtZalrsc] in {
|
|
|
|
let Size = 20 in
|
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def PseudoAtomicLoadNand32 : PseudoAMO;
|
|
defm : PseudoAMOPat<"atomic_load_nand_i32", PseudoAtomicLoadNand32>;
|
|
|
|
let Size = 28 in {
|
|
def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
|
|
def PseudoMaskedAtomicLoadAdd32 : PseudoMaskedAMO;
|
|
def PseudoMaskedAtomicLoadSub32 : PseudoMaskedAMO;
|
|
}
|
|
let Size = 32 in {
|
|
def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAMO;
|
|
}
|
|
let Size = 44 in {
|
|
def PseudoMaskedAtomicLoadMax32 : PseudoMaskedAMOMinMax;
|
|
def PseudoMaskedAtomicLoadMin32 : PseudoMaskedAMOMinMax;
|
|
}
|
|
let Size = 36 in {
|
|
def PseudoMaskedAtomicLoadUMax32 : PseudoMaskedAMOUMinUMax;
|
|
def PseudoMaskedAtomicLoadUMin32 : PseudoMaskedAMOUMinUMax;
|
|
}
|
|
|
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg,
|
|
PseudoMaskedAtomicSwap32>;
|
|
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_add,
|
|
PseudoMaskedAtomicLoadAdd32>;
|
|
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_sub,
|
|
PseudoMaskedAtomicLoadSub32>;
|
|
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_nand,
|
|
PseudoMaskedAtomicLoadNand32>;
|
|
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_max,
|
|
PseudoMaskedAtomicLoadMax32>;
|
|
def : PseudoMaskedAMOMinMaxPat<int_riscv_masked_atomicrmw_min,
|
|
PseudoMaskedAtomicLoadMin32>;
|
|
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umax,
|
|
PseudoMaskedAtomicLoadUMax32>;
|
|
def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin,
|
|
PseudoMaskedAtomicLoadUMin32>;
|
|
} // Predicates = [HasStdExtZalrsc]
|
|
|
|
let Predicates = [HasStdExtZalrsc, IsRV64] in {
|
|
|
|
let Size = 20 in
|
|
def PseudoAtomicLoadNand64 : PseudoAMO;
|
|
defm : PseudoAMOPat<"atomic_load_nand_i64", PseudoAtomicLoadNand64, i64>;
|
|
} // Predicates = [HasStdExtZalrsc, IsRV64]
|
|
|
|
|
|
/// Compare and exchange
|
|
|
|
class PseudoCmpXchg
|
|
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
|
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, ordering:$ordering), []> {
|
|
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let hasSideEffects = 0;
|
|
let Size = 16;
|
|
}
|
|
|
|
// Ordering constants must be kept in sync with the AtomicOrdering enum in
|
|
// AtomicOrdering.h.
|
|
multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst,
|
|
ValueType vt = XLenVT> {
|
|
def : Pat<(vt (!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new)),
|
|
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>;
|
|
def : Pat<(vt (!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new)),
|
|
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>;
|
|
def : Pat<(vt (!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new)),
|
|
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 5)>;
|
|
def : Pat<(vt (!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new)),
|
|
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 6)>;
|
|
def : Pat<(vt (!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new)),
|
|
(CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
|
|
}
|
|
|
|
let Predicates = [HasStdExtZalrsc, NoStdExtZacas] in {
|
|
def PseudoCmpXchg32 : PseudoCmpXchg;
|
|
defm : PseudoCmpXchgPat<"atomic_cmp_swap_i32", PseudoCmpXchg32>;
|
|
}
|
|
|
|
let Predicates = [HasStdExtZalrsc, NoStdExtZacas, IsRV64] in {
|
|
def PseudoCmpXchg64 : PseudoCmpXchg;
|
|
defm : PseudoCmpXchgPat<"atomic_cmp_swap_i64", PseudoCmpXchg64, i64>;
|
|
}
|
|
|
|
let Predicates = [HasStdExtZalrsc] in {
|
|
def PseudoMaskedCmpXchg32
|
|
: Pseudo<(outs GPR:$res, GPR:$scratch),
|
|
(ins GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask,
|
|
ordering:$ordering), []> {
|
|
let Constraints = "@earlyclobber $res,@earlyclobber $scratch";
|
|
let mayLoad = 1;
|
|
let mayStore = 1;
|
|
let hasSideEffects = 0;
|
|
let Size = 32;
|
|
}
|
|
|
|
def : Pat<(XLenVT (int_riscv_masked_cmpxchg
|
|
(XLenVT GPR:$addr), (XLenVT GPR:$cmpval), (XLenVT GPR:$newval),
|
|
(XLenVT GPR:$mask), (XLenVT timm:$ordering))),
|
|
(PseudoMaskedCmpXchg32
|
|
GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
|
|
} // Predicates = [HasStdExtZalrsc]
|