derek.holloway
7502bf64a4
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50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm64_32-apple-darwin -O0 -fast-isel -verify-machineinstrs \
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; RUN: -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-collect-loh=0 \
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; RUN: < %s | FileCheck %s
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; FastISel doesn't support cstexprs as operands here, but make
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; sure it knows to fallback, at least.
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define void @atomic_store_cstexpr_addr(i32 %val) #0 {
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; CHECK-LABEL: atomic_store_cstexpr_addr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: adrp x8, _g@PAGE
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; CHECK-NEXT: add x8, x8, _g@PAGEOFF
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; CHECK-NEXT: ; kill: def $w1 killed $w8 killed $x8
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; CHECK-NEXT: adrp x8, _g@PAGE
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; CHECK-NEXT: add x8, x8, _g@PAGEOFF
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; CHECK-NEXT: stlr w0, [x8]
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; CHECK-NEXT: ret
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store atomic i32 %val, ptr inttoptr (i32 ptrtoint (ptr @g to i32) to ptr) release, align 4
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ret void
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}
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define i32 @cmpxchg_cstexpr_addr(i32 %cmp, i32 %new, ptr %ps) #0 {
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; CHECK-LABEL: cmpxchg_cstexpr_addr:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: adrp x10, _g@PAGE
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; CHECK-NEXT: add x10, x10, _g@PAGEOFF
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; CHECK-NEXT: LBB1_1: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldaxr w0, [x10]
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; CHECK-NEXT: cmp w0, w8
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; CHECK-NEXT: b.ne LBB1_3
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; CHECK-NEXT: ; %bb.2: ; in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: stlxr w9, w1, [x10]
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; CHECK-NEXT: cbnz w9, LBB1_1
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; CHECK-NEXT: LBB1_3:
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; CHECK-NEXT: subs w8, w0, w8
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%tmp0 = cmpxchg ptr inttoptr (i32 ptrtoint (ptr @g to i32) to ptr), i32 %cmp, i32 %new seq_cst seq_cst
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%tmp1 = extractvalue { i32, i1 } %tmp0, 0
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%tmp2 = extractvalue { i32, i1 } %tmp0, 1
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%tmp3 = zext i1 %tmp2 to i32
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store i32 %tmp3, ptr %ps
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ret i32 %tmp1
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}
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@g = global i32 0
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