derek.holloway
7502bf64a4
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95 lines
3.1 KiB
LLVM
95 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s
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define fastcc void @test_sdot_v4i8(ptr noalias nocapture %0, ptr noalias nocapture readonly %1, ptr noalias nocapture readonly %2) {
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; CHECK-LABEL: test_sdot_v4i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr w8, [x2]
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: dup v0.2s, wzr
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmov s2, w9
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; CHECK-NEXT: sdot v0.2s, v1.8b, v2.8b
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ret
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entry:
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%3 = load i8, ptr %1, align 1
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%4 = sext i8 %3 to i32
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%5 = load i8, ptr %2, align 1
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%6 = sext i8 %5 to i32
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%7 = mul nsw i32 %6, %4
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%8 = getelementptr inbounds i8, ptr %1, i64 1
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%9 = load i8, ptr %8, align 1
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%10 = sext i8 %9 to i32
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%11 = getelementptr inbounds i8, ptr %2, i64 1
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%12 = load i8, ptr %11, align 1
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%13 = sext i8 %12 to i32
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%14 = mul nsw i32 %13, %10
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%15 = add nsw i32 %14, %7
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%16 = getelementptr inbounds i8, ptr %1, i64 2
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%17 = load i8, ptr %16, align 1
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%18 = sext i8 %17 to i32
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%19 = getelementptr inbounds i8, ptr %2, i64 2
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%20 = load i8, ptr %19, align 1
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%21 = sext i8 %20 to i32
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%22 = mul nsw i32 %21, %18
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%23 = add nsw i32 %22, %15
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%24 = getelementptr inbounds i8, ptr %1, i64 3
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%25 = load i8, ptr %24, align 1
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%26 = sext i8 %25 to i32
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%27 = getelementptr inbounds i8, ptr %2, i64 3
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%28 = load i8, ptr %27, align 1
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%29 = sext i8 %28 to i32
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%30 = mul nsw i32 %29, %26
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%31 = add nsw i32 %30, %23
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store i32 %31, ptr %0, align 64
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ret void
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}
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define fastcc void @test_udot_v4i8(ptr noalias nocapture %0, ptr noalias nocapture readonly %1, ptr noalias nocapture readonly %2) {
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; CHECK-LABEL: test_udot_v4i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ldr w8, [x2]
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; CHECK-NEXT: ldr w9, [x1]
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; CHECK-NEXT: dup v0.2s, wzr
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: fmov s2, w9
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; CHECK-NEXT: udot v0.2s, v1.8b, v2.8b
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: str w8, [x0]
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; CHECK-NEXT: ret
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entry:
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%3 = load i8, ptr %1, align 1
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%4 = zext i8 %3 to i32
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%5 = load i8, ptr %2, align 1
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%6 = zext i8 %5 to i32
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%7 = mul nsw i32 %6, %4
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%8 = getelementptr inbounds i8, ptr %1, i64 1
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%9 = load i8, ptr %8, align 1
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%10 = zext i8 %9 to i32
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%11 = getelementptr inbounds i8, ptr %2, i64 1
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%12 = load i8, ptr %11, align 1
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%13 = zext i8 %12 to i32
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%14 = mul nsw i32 %13, %10
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%15 = add nsw i32 %14, %7
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%16 = getelementptr inbounds i8, ptr %1, i64 2
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%17 = load i8, ptr %16, align 1
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%18 = zext i8 %17 to i32
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%19 = getelementptr inbounds i8, ptr %2, i64 2
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%20 = load i8, ptr %19, align 1
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%21 = zext i8 %20 to i32
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%22 = mul nsw i32 %21, %18
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%23 = add nsw i32 %22, %15
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%24 = getelementptr inbounds i8, ptr %1, i64 3
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%25 = load i8, ptr %24, align 1
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%26 = zext i8 %25 to i32
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%27 = getelementptr inbounds i8, ptr %2, i64 3
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%28 = load i8, ptr %27, align 1
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%29 = zext i8 %28 to i32
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%30 = mul nsw i32 %29, %26
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%31 = add nsw i32 %30, %23
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store i32 %31, ptr %0, align 64
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ret void
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}
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