derek.holloway
7502bf64a4
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120 lines
2.9 KiB
LLVM
120 lines
2.9 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
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; CHECK-NEXT: __LLVM_StackMaps:
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; Header
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .short 0
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; Num Functions
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; CHECK-NEXT: .long 1
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; Num LargeConstants
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; CHECK-NEXT: .long 0
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; Num Callsites
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; CHECK-NEXT: .long 1
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; Functions and stack size
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; CHECK-NEXT: .quad _stackmap_liveness
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; CHECK-NEXT: .quad 16
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; Test that the return register is recognized as an live-out.
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define i64 @stackmap_liveness(i1 %c) {
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; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .short 0
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; Padding
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: .short 0
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; Num LiveOut Entries: 20
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; CHECK-NEXT: .short 20
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; LiveOut Entry 1: X0
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; CHECK-NEXT: .short 0
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 2:
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; CHECK-NEXT: .short 19
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 3:
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; CHECK-NEXT: .short 20
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 4:
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; CHECK-NEXT: .short 21
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 5:
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; CHECK-NEXT: .short 22
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 6:
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; CHECK-NEXT: .short 23
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 7:
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; CHECK-NEXT: .short 24
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 8:
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; CHECK-NEXT: .short 25
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 9:
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; CHECK-NEXT: .short 26
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 10:
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; CHECK-NEXT: .short 27
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 11:
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; CHECK-NEXT: .short 28
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 12: SP
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; CHECK-NEXT: .short 31
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 13:
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; CHECK-NEXT: .short 72
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 14:
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; CHECK-NEXT: .short 73
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 15:
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; CHECK-NEXT: .short 74
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 16:
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; CHECK-NEXT: .short 75
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 17:
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; CHECK-NEXT: .short 76
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 18:
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; CHECK-NEXT: .short 77
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 19:
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; CHECK-NEXT: .short 78
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; LiveOut Entry 20:
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; CHECK-NEXT: .short 79
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; CHECK-NEXT: .byte 0
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; CHECK-NEXT: .byte 8
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; Align
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; CHECK-NEXT: .p2align 3
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%1 = select i1 %c, i64 1, i64 2
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call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, ptr null, i32 0)
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ret i64 %1
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}
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declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
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