derek.holloway
7502bf64a4
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60 lines
2.3 KiB
LLVM
60 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s
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declare hidden ptr addrspace(1) @ext(ptr addrspace(1))
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define ptr addrspace(1) @call_assert_align() #0 {
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; CHECK-LABEL: call_assert_align:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s16, s33
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; CHECK-NEXT: s_mov_b32 s33, s32
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; CHECK-NEXT: s_or_saveexec_b64 s[18:19], -1
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; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
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; CHECK-NEXT: s_mov_b64 exec, s[18:19]
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; CHECK-NEXT: v_writelane_b32 v40, s16, 2
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; CHECK-NEXT: v_writelane_b32 v40, s30, 0
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; CHECK-NEXT: s_addk_i32 s32, 0x400
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; CHECK-NEXT: v_writelane_b32 v40, s31, 1
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: v_readlane_b32 s30, v40, 0
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; CHECK-NEXT: global_store_dword v[0:1], v2, off
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_readlane_b32 s31, v40, 1
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; CHECK-NEXT: s_mov_b32 s32, s33
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; CHECK-NEXT: v_readlane_b32 s4, v40, 2
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; CHECK-NEXT: s_or_saveexec_b64 s[6:7], -1
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; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
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; CHECK-NEXT: s_mov_b64 exec, s[6:7]
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; CHECK-NEXT: s_mov_b32 s33, s4
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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%call = call align 4 ptr addrspace(1) @ext(ptr addrspace(1) null)
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store volatile i32 0, ptr addrspace(1) %call
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ret ptr addrspace(1) %call
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}
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define ptr addrspace(1) @tail_call_assert_align() #0 {
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; CHECK-LABEL: tail_call_assert_align:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_getpc_b64 s[16:17]
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; CHECK-NEXT: s_add_u32 s16, s16, ext@rel32@lo+4
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; CHECK-NEXT: s_addc_u32 s17, s17, ext@rel32@hi+12
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; CHECK-NEXT: v_mov_b32_e32 v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_setpc_b64 s[16:17]
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entry:
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%call = tail call align 4 ptr addrspace(1) @ext(ptr addrspace(1) null)
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ret ptr addrspace(1) %call
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}
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attributes #0 = { nounwind }
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