derek.holloway
7502bf64a4
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64 lines
2.6 KiB
LLVM
64 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefix=GCN
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define i32 @test(i32 %val, i32 %cond) {
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; GCN-LABEL: test:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_xor_saveexec_b32 s4, -1
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; GCN-NEXT: buffer_store_dword v2, off, s[0:3], s32 ; 4-byte Folded Spill
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; GCN-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
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; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
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; GCN-NEXT: s_mov_b32 exec_lo, s4
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; GCN-NEXT: s_or_saveexec_b32 s4, -1
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v0, s4
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; GCN-NEXT: v_mov_b32_dpp v2, v3 row_xmask:1 row_mask:0xf bank_mask:0xf
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; GCN-NEXT: s_mov_b32 exec_lo, s4
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; GCN-NEXT: v_mov_b32_e32 v5, 0
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; GCN-NEXT: v_mov_b32_e32 v4, v2
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
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; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GCN-NEXT: ; %bb.1: ; %if
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; GCN-NEXT: s_or_saveexec_b32 s5, -1
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_cndmask_b32_e64 v3, 0, v0, s5
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; GCN-NEXT: v_mov_b32_dpp v2, v3 row_xmask:1 row_mask:0xf bank_mask:0xf
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; GCN-NEXT: s_mov_b32 exec_lo, s5
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; GCN-NEXT: v_mov_b32_e32 v5, v2
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; GCN-NEXT: ; %bb.2: ; %end
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: v_add_nc_u32_e32 v0, v4, v5
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; GCN-NEXT: s_xor_saveexec_b32 s4, -1
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; GCN-NEXT: s_clause 0x1 ; 8-byte Folded Reload
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; GCN-NEXT: buffer_load_dword v2, off, s[0:3], s32
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; GCN-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4
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; GCN-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)
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; GCN-NEXT: s_mov_b32 exec_lo, s4
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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; %x = subgroup operation over all lanes.
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%x1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %val, i32 0)
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%x2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %x1, i32 353, i32 15, i32 15, i1 false)
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%x3 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %x2)
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%cmp = icmp eq i32 %cond, 0
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br i1 %cmp, label %if, label %end
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if:
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; %y = subgroup operations over lanes satisfying %cond.
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%y1 = call i32 @llvm.amdgcn.set.inactive.i32(i32 %val, i32 0)
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%y2 = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %y1, i32 353, i32 15, i32 15, i1 false)
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%y3 = call i32 @llvm.amdgcn.strict.wwm.i32(i32 %y2)
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br label %end
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end:
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%y = phi i32 [0, %entry], [%y3, %if]
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%ret = add i32 %x3, %y
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ret i32 %ret
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}
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declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32)
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg)
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declare i32 @llvm.amdgcn.strict.wwm.i32(i32)
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