derek.holloway
7502bf64a4
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234 lines
8.8 KiB
LLVM
234 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
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; Demonstrate that the conversion of bitmasks affecting the sign bit on integers to srcmods
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; does not apply to canonicalizing instructions.
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define double @v_uitofp_i32_to_f64_abs(i32 %arg0) nounwind {
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; GCN-LABEL: v_uitofp_i32_to_f64_abs:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
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; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_uitofp_i32_to_f64_abs:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%arg0.abs = and i32 %arg0, u0x7fffffff
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%cvt = uitofp i32 %arg0.abs to double
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ret double %cvt
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}
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define double @v_uitofp_i32_to_f64_neg(i32 %arg0) nounwind {
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; GCN-LABEL: v_uitofp_i32_to_f64_neg:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_and_b32_e32 v0, 0x80000000, v0
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; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: v_uitofp_i32_to_f64_neg:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_and_b32_e32 v0, 0x80000000, v0
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; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%arg0.neg = and i32 %arg0, u0x80000000
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%cvt = uitofp i32 %arg0.neg to double
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ret double %cvt
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}
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define double @s_uitofp_i32_to_f64_abs(i32 inreg %arg0) nounwind {
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; GCN-LABEL: s_uitofp_i32_to_f64_abs:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_bitset0_b32 s16, 31
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; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], s16
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: s_uitofp_i32_to_f64_abs:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_bitset0_b32 s0, 31
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%arg0.abs = and i32 %arg0, u0x7fffffff
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%cvt = uitofp i32 %arg0.abs to double
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ret double %cvt
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}
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define double @s_uitofp_i32_to_f64_neg(i32 inreg %arg0) nounwind {
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; GCN-LABEL: s_uitofp_i32_to_f64_neg:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_and_b32 s4, s16, 0x80000000
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; GCN-NEXT: v_cvt_f64_u32_e32 v[0:1], s4
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; GCN-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: s_uitofp_i32_to_f64_neg:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: s_and_b32 s0, s0, 0x80000000
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_cvt_f64_u32_e32 v[0:1], s0
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%arg0.neg = and i32 %arg0, u0x80000000
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%cvt = uitofp i32 %arg0.neg to double
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ret double %cvt
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}
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define half @v_uitofp_i16_to_f16_abs(i16 %arg0) nounwind {
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; GFX7-LABEL: v_uitofp_i16_to_f16_abs:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX7-NEXT: v_cvt_f32_u32_e32 v0, v0
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; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: v_uitofp_i16_to_f16_abs:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX9-NEXT: v_cvt_f16_u16_e32 v0, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-TRUE16-LABEL: v_uitofp_i16_to_f16_abs:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: v_uitofp_i16_to_f16_abs:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0
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; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%arg0.abs = and i16 %arg0, u0x7fff
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%cvt = uitofp i16 %arg0.abs to half
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ret half %cvt
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}
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define half @v_uitofp_i16_to_f16_neg(i16 %arg0) nounwind {
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; GFX7-LABEL: v_uitofp_i16_to_f16_neg:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: v_and_b32_e32 v0, 0x8000, v0
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; GFX7-NEXT: v_cvt_f32_u32_e32 v0, v0
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; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: v_uitofp_i16_to_f16_neg:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
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; GFX9-NEXT: v_cvt_f16_u16_e32 v0, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-TRUE16-LABEL: v_uitofp_i16_to_f16_neg:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, v0.l
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, v0.l
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: v_uitofp_i16_to_f16_neg:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, v0
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; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%arg0.neg = and i16 %arg0, u0x8000
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%cvt = uitofp i16 %arg0.neg to half
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ret half %cvt
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}
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define half @s_uitofp_i16_to_f16_abs(i16 inreg %arg0) nounwind {
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; GFX7-LABEL: s_uitofp_i16_to_f16_abs:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_and_b32 s4, s16, 0x7fff
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; GFX7-NEXT: v_cvt_f32_u32_e32 v0, s4
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; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: s_uitofp_i16_to_f16_abs:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, s16, 0x7fff
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; GFX9-NEXT: v_cvt_f16_u16_e32 v0, s4
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-TRUE16-LABEL: s_uitofp_i16_to_f16_abs:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, s0
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: s_uitofp_i16_to_f16_abs:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0x7fff
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, s0
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; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%arg0.abs = and i16 %arg0, u0x7fff
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%cvt = uitofp i16 %arg0.abs to half
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ret half %cvt
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}
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define half @s_uitofp_i16_to_f16_neg(i16 inreg %arg0) nounwind {
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; GFX7-LABEL: s_uitofp_i16_to_f16_neg:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_and_b32 s4, s16, 0x8000
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; GFX7-NEXT: v_cvt_f32_u32_e32 v0, s4
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; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: s_uitofp_i16_to_f16_neg:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, s16, 0x8000
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; GFX9-NEXT: v_cvt_f16_u16_e32 v0, s4
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-TRUE16-LABEL: s_uitofp_i16_to_f16_neg:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0x8000
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-TRUE16-NEXT: v_cvt_f16_u16_e32 v0.l, s0
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; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-FAKE16-LABEL: s_uitofp_i16_to_f16_neg:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0x8000
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-FAKE16-NEXT: v_cvt_f16_u16_e32 v0, s0
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; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%arg0.neg = and i16 %arg0, u0x8000
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%cvt = uitofp i16 %arg0.neg to half
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ret half %cvt
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}
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