derek.holloway
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53 lines
2.4 KiB
LLVM
53 lines
2.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}load_idx_idy:
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; GCN-NOT: global_load
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; GCN: s_load_dword [[ID_XY:s[0-9]+]], s[4:5], 0x4
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; GCN-NOT: global_load
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; GCN: s_lshr_b32 [[ID_Y:s[0-9]+]], [[ID_XY]], 16
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; GCN: s_add_i32 [[ID_SUM:s[0-9]+]], [[ID_Y]], [[ID_XY]]
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; GCN: s_and_b32 s{{[0-9]+}}, [[ID_SUM]], 0xffff
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define protected amdgpu_kernel void @load_idx_idy(ptr addrspace(1) %out) {
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entry:
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%disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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%gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 4
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%id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x
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%gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 6
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%id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y
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%add = add nuw nsw i16 %id_y, %id_x
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%conv = zext i16 %add to i32
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store i32 %conv, ptr addrspace(1) %out, align 4
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ret void
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}
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; A little more complicated case where more sub-dword loads could be coalesced
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; if they are not widening earlier.
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; GCN-LABEL: {{^}}load_4i16:
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; GCN: s_load_dwordx2 s[[[D0:[0-9]+]]:[[D1:[0-9]+]]], s[4:5], 0x4
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; GCN-NOT: s_load_dword {{s[0-9]+}}, s[4:5], 0x4
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; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D0]], 16
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; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s[[D1]], 16
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; GCN: s_endpgm
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define protected amdgpu_kernel void @load_4i16(ptr addrspace(1) %out) {
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entry:
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%disp = tail call align 4 dereferenceable(64) ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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%gep_x = getelementptr i8, ptr addrspace(4) %disp, i64 4
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%id_x = load i16, ptr addrspace(4) %gep_x, align 4, !invariant.load !0 ; load workgroup size x
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%gep_y = getelementptr i8, ptr addrspace(4) %disp, i64 6
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%id_y = load i16, ptr addrspace(4) %gep_y, align 2, !invariant.load !0 ; load workgroup size y
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%gep_z = getelementptr i8, ptr addrspace(4) %disp, i64 8
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%id_z = load i16, ptr addrspace(4) %gep_z, align 4, !invariant.load !0 ; load workgroup size x
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%gep_w = getelementptr i8, ptr addrspace(4) %disp, i64 10
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%id_w = load i16, ptr addrspace(4) %gep_w, align 2, !invariant.load !0 ; load workgroup size y
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%add = add nuw nsw i16 %id_y, %id_x
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%add2 = add nuw nsw i16 %id_z, %id_w
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%add3 = add nuw nsw i16 %add, %add2
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%conv = zext i16 %add3 to i32
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store i32 %conv, ptr addrspace(1) %out, align 4
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ret void
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}
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declare ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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!0 = !{!0}
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