derek.holloway
7502bf64a4
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271 lines
6.5 KiB
LLVM
271 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=avr | FileCheck %s
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define i8 @rotl8_1(i8 %x) {
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; CHECK-LABEL: rotl8_1:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 1)
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ret i8 %0
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}
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define i8 @rotl8_3(i8 %x) {
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; CHECK-LABEL: rotl8_3:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: swap r24
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
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ret i8 %0
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}
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define i8 @rotl8_5(i8 %x) {
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; CHECK-LABEL: rotl8_5:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: swap r24
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)
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ret i8 %0
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}
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define i8 @rotl8_7(i8 %x) {
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; CHECK-LABEL: rotl8_7:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)
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ret i8 %0
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}
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define i8 @rotl8_dyn(i8 %x, i8 %y) {
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; CHECK-LABEL: rotl8_dyn:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: andi r22, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brmi .LBB4_2
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; CHECK-NEXT: .LBB4_1: ; %start
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brpl .LBB4_1
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; CHECK-NEXT: .LBB4_2: ; %start
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)
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ret i8 %0
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}
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define i8 @rotr8_1(i8 %x) {
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; CHECK-LABEL: rotr8_1:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 1)
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ret i8 %0
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}
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define i8 @rotr8_3(i8 %x) {
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; CHECK-LABEL: rotr8_3:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: swap r24
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
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ret i8 %0
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}
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define i8 @rotr8_5(i8 %x) {
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; CHECK-LABEL: rotr8_5:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: swap r24
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 5)
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ret i8 %0
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}
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define i8 @rotr8_7(i8 %x) {
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; CHECK-LABEL: rotr8_7:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: adc r24, r1
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)
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ret i8 %0
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}
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define i8 @rotr8_dyn(i8 %x, i8 %y) {
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; CHECK-LABEL: rotr8_dyn:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: andi r22, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brmi .LBB9_2
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; CHECK-NEXT: .LBB9_1: ; %start
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: bst r24, 0
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: bld r24, 7
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; CHECK-NEXT: dec r22
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; CHECK-NEXT: brpl .LBB9_1
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; CHECK-NEXT: .LBB9_2: ; %start
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; CHECK-NEXT: ret
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start:
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%0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)
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ret i8 %0
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}
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define i16 @rotl16(i16 %x) {
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; CHECK-LABEL: rotl16:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: mov r18, r24
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; CHECK-NEXT: mov r19, r25
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; CHECK-NEXT: lsl r18
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; CHECK-NEXT: rol r19
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; CHECK-NEXT: lsl r18
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; CHECK-NEXT: rol r19
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; CHECK-NEXT: mov r24, r25
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; CHECK-NEXT: swap r24
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; CHECK-NEXT: andi r24, 15
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; CHECK-NEXT: clr r25
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; CHECK-NEXT: lsr r24
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; CHECK-NEXT: lsr r24
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; CHECK-NEXT: or r24, r18
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; CHECK-NEXT: or r25, r19
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; CHECK-NEXT: ret
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start:
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%0 = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 2)
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ret i16 %0
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}
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define i16 @rotr16(i16 %x) {
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; CHECK-LABEL: rotr16:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: mov r18, r24
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; CHECK-NEXT: mov r19, r25
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; CHECK-NEXT: lsr r19
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; CHECK-NEXT: ror r18
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; CHECK-NEXT: lsr r19
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; CHECK-NEXT: ror r18
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; CHECK-NEXT: mov r25, r24
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; CHECK-NEXT: swap r25
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; CHECK-NEXT: andi r25, 240
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; CHECK-NEXT: clr r24
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; CHECK-NEXT: lsl r25
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; CHECK-NEXT: lsl r25
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; CHECK-NEXT: or r24, r18
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; CHECK-NEXT: or r25, r19
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; CHECK-NEXT: ret
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start:
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%0 = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 2)
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ret i16 %0
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}
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define i32 @rotl32(i32 %x) {
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; CHECK-LABEL: rotl32:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: mov r20, r22
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; CHECK-NEXT: mov r21, r23
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; CHECK-NEXT: lsl r20
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; CHECK-NEXT: rol r21
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; CHECK-NEXT: lsl r20
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; CHECK-NEXT: rol r21
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; CHECK-NEXT: mov r18, r24
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; CHECK-NEXT: mov r19, r25
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; CHECK-NEXT: mov r18, r19
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; CHECK-NEXT: swap r18
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; CHECK-NEXT: andi r18, 15
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; CHECK-NEXT: clr r19
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; CHECK-NEXT: lsr r18
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; CHECK-NEXT: lsr r18
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; CHECK-NEXT: or r18, r20
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; CHECK-NEXT: or r19, r21
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: rol r25
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; CHECK-NEXT: lsl r24
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; CHECK-NEXT: rol r25
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; CHECK-NEXT: mov r22, r23
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; CHECK-NEXT: swap r22
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; CHECK-NEXT: andi r22, 15
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; CHECK-NEXT: clr r23
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; CHECK-NEXT: lsr r22
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; CHECK-NEXT: lsr r22
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; CHECK-NEXT: or r24, r22
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; CHECK-NEXT: or r25, r23
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; CHECK-NEXT: mov r22, r18
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; CHECK-NEXT: mov r23, r19
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; CHECK-NEXT: ret
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start:
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%0 = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 2)
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ret i32 %0
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}
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define i32 @rotr32(i32 %x) {
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; CHECK-LABEL: rotr32:
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; CHECK: ; %bb.0: ; %start
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; CHECK-NEXT: mov r20, r22
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; CHECK-NEXT: mov r21, r23
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; CHECK-NEXT: lsr r21
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; CHECK-NEXT: ror r20
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; CHECK-NEXT: lsr r21
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; CHECK-NEXT: ror r20
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; CHECK-NEXT: mov r18, r24
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; CHECK-NEXT: mov r19, r25
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; CHECK-NEXT: mov r19, r18
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; CHECK-NEXT: swap r19
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; CHECK-NEXT: andi r19, 240
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; CHECK-NEXT: clr r18
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; CHECK-NEXT: lsl r19
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; CHECK-NEXT: lsl r19
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; CHECK-NEXT: or r18, r20
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; CHECK-NEXT: or r19, r21
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; CHECK-NEXT: lsr r25
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: lsr r25
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; CHECK-NEXT: ror r24
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; CHECK-NEXT: mov r23, r22
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; CHECK-NEXT: swap r23
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; CHECK-NEXT: andi r23, 240
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; CHECK-NEXT: clr r22
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; CHECK-NEXT: lsl r23
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; CHECK-NEXT: lsl r23
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; CHECK-NEXT: or r24, r22
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; CHECK-NEXT: or r25, r23
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; CHECK-NEXT: mov r22, r18
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; CHECK-NEXT: mov r23, r19
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; CHECK-NEXT: ret
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start:
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%0 = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 2)
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ret i32 %0
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}
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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