derek.holloway
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35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; Check if extract_subvectors is handled properly in Hexagon backend when the
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; the source vector is a vector-pair and result vector is not hvx vector size.
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; https://github.com/llvm/llvm-project/issues/128775
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;
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; Example of such a case:
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; ...
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; t2: v64i32,ch = CopyFromReg t0, Register:v64i32 %0
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; t17: v2i32 = extract_subvector t2, Constant:i32<4>
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; ...
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; RUN: llc -mtriple=hexagon -mattr="hvx-length128b" < %s | FileCheck %s
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; CHECK-LABEL: extract_subvec:
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; CHECK: r29 = and(r29,#-128)
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; CHECK: [[R1:r([0-9]+)]] = add(r29,#0)
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; CHECK: vmem([[R1]]+#0) = v0
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; CHECK-DAG: r[[R4:[0-9]+]] = memw([[R1]]+#0)
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; CHECK-DAG: r[[R5:[0-9]+]] = memw([[R1]]+#4)
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; CHECK-DAG: r[[R6:[0-9]+]] = memw([[R1]]+#8)
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; CHECK-DAG: r[[R7:[0-9]+]] = memw([[R1]]+#12)
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; CHECK-DAG: r[[R8:[0-9]+]] = memw([[R1]]+#16)
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; CHECK-DAG: r[[R9:[0-9]+]] = memw([[R1]]+#20)
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; CHECK-DAG: r[[R2:[0-9]+]] = memw([[R1]]+#24)
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; CHECK-DAG: r[[R3:[0-9]+]] = memw([[R1]]+#28)
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; CHECK-DAG: memd(r0+#0) = r[[R5]]:[[R4]]
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; CHECK-DAG: memd(r0+#8) = r[[R7]]:[[R6]]
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; CHECK-DAG: memd(r0+#16) = r[[R9]]:[[R8]]
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; CHECK-DAG: memw(r0+#24) = r[[R2]]
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define void @extract_subvec(<56 x i32> %val, ptr %buf) {
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entry:
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%split = shufflevector <56 x i32> %val, <56 x i32> zeroinitializer, <7 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
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store <7 x i32> %split, ptr %buf, align 32
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ret void
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}
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