derek.holloway
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116 lines
3.7 KiB
LLVM
116 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 {
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; CHECK-LABEL: testi1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: crmove 20, 1
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; CHECK-NEXT: andi. 3, 4, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: crand 20, 20, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: isel 3, 4, 3, 20
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; CHECK-NEXT: blr
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;
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; CHECK-NO-ISEL-LABEL: testi1:
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; CHECK-NO-ISEL: # %bb.0: # %entry
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; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
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; CHECK-NO-ISEL-NEXT: crmove 20, 1
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; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
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; CHECK-NO-ISEL-NEXT: li 3, 1
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; CHECK-NO-ISEL-NEXT: #APP
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; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
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; CHECK-NO-ISEL-NEXT: #NO_APP
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; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
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; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
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; CHECK-NO-ISEL-NEXT: li 3, 0
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; CHECK-NO-ISEL-NEXT: blr
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0
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%1 = and i8 %0, 1
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%tobool3 = icmp ne i8 %1, 0
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ret i1 %tobool3
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}
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define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 {
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; CHECK-LABEL: testi32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: crmove 20, 1
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; CHECK-NEXT: andi. 3, 4, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, -1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: crand 20, 20, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: isel 3, 4, 3, 20
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; CHECK-NEXT: blr
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;
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; CHECK-NO-ISEL-LABEL: testi32:
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; CHECK-NO-ISEL: # %bb.0: # %entry
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; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
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; CHECK-NO-ISEL-NEXT: crmove 20, 1
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; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
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; CHECK-NO-ISEL-NEXT: li 3, -1
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; CHECK-NO-ISEL-NEXT: #APP
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; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
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; CHECK-NO-ISEL-NEXT: #NO_APP
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; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
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; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
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; CHECK-NO-ISEL-NEXT: li 3, 0
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; CHECK-NO-ISEL-NEXT: blr
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entry:
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%0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0
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ret i32 %0
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; The ABI sign_extend should combine with the any_extend from the asm result,
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; and the result will be 0 or -1. This highlights the fact that only the first
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; bit is meaningful.
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}
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define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 {
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; CHECK-LABEL: testi8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: andi. 3, 3, 1
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; CHECK-NEXT: crmove 20, 1
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; CHECK-NEXT: andi. 3, 4, 1
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: #APP
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; CHECK-NEXT: crand 20, 20, 1
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: isel 3, 4, 3, 20
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; CHECK-NEXT: blr
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;
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; CHECK-NO-ISEL-LABEL: testi8:
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; CHECK-NO-ISEL: # %bb.0: # %entry
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; CHECK-NO-ISEL-NEXT: andi. 3, 3, 1
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; CHECK-NO-ISEL-NEXT: crmove 20, 1
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; CHECK-NO-ISEL-NEXT: andi. 3, 4, 1
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; CHECK-NO-ISEL-NEXT: li 3, 1
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; CHECK-NO-ISEL-NEXT: #APP
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; CHECK-NO-ISEL-NEXT: crand 20, 20, 1
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; CHECK-NO-ISEL-NEXT: #NO_APP
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; CHECK-NO-ISEL-NEXT: bclr 12, 20, 0
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; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
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; CHECK-NO-ISEL-NEXT: li 3, 0
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; CHECK-NO-ISEL-NEXT: blr
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entry:
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%0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0
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ret i8 %0
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}
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attributes #0 = { nounwind "target-features"="+crbits" }
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