derek.holloway
7502bf64a4
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220 lines
6.2 KiB
LLVM
220 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32ZB
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64ZB
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32ZB
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV64ZB
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define i16 @test_bswap_srli_7_bswap_i16(i16 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_7_bswap_i16:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: rev8 a0, a0
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; RV32ZB-NEXT: srli a0, a0, 23
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; RV32ZB-NEXT: rev8 a0, a0
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; RV32ZB-NEXT: srli a0, a0, 16
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_7_bswap_i16:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: rev8 a0, a0
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; RV64ZB-NEXT: srli a0, a0, 55
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; RV64ZB-NEXT: rev8 a0, a0
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; RV64ZB-NEXT: srli a0, a0, 48
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; RV64ZB-NEXT: ret
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%1 = call i16 @llvm.bswap.i16(i16 %a)
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%2 = lshr i16 %1, 7
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%3 = call i16 @llvm.bswap.i16(i16 %2)
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ret i16 %3
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}
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define i16 @test_bswap_srli_8_bswap_i16(i16 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_8_bswap_i16:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a0, a0, 8
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_8_bswap_i16:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slli a0, a0, 8
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; RV64ZB-NEXT: ret
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%1 = call i16 @llvm.bswap.i16(i16 %a)
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%2 = lshr i16 %1, 8
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%3 = call i16 @llvm.bswap.i16(i16 %2)
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ret i16 %3
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}
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define i32 @test_bswap_srli_8_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_8_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a0, a0, 8
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_8_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slliw a0, a0, 8
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = lshr i32 %1, 8
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i32 @test_bswap_srli_16_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_16_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a0, a0, 16
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_16_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slliw a0, a0, 16
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = lshr i32 %1, 16
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i32 @test_bswap_srli_24_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_24_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a0, a0, 24
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_24_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slliw a0, a0, 24
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = lshr i32 %1, 24
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i64 @test_bswap_srli_48_bswap_i64(i64 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_srli_48_bswap_i64:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a1, a0, 16
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; RV32ZB-NEXT: li a0, 0
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_srli_48_bswap_i64:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slli a0, a0, 48
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; RV64ZB-NEXT: ret
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%1 = call i64 @llvm.bswap.i64(i64 %a)
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%2 = lshr i64 %1, 48
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%3 = call i64 @llvm.bswap.i64(i64 %2)
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ret i64 %3
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}
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define i16 @test_bswap_shli_7_bswap_i16(i16 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_7_bswap_i16:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: rev8 a0, a0
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; RV32ZB-NEXT: srli a0, a0, 16
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; RV32ZB-NEXT: slli a0, a0, 7
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; RV32ZB-NEXT: rev8 a0, a0
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; RV32ZB-NEXT: srli a0, a0, 16
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_7_bswap_i16:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: rev8 a0, a0
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; RV64ZB-NEXT: srli a0, a0, 48
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; RV64ZB-NEXT: slli a0, a0, 7
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; RV64ZB-NEXT: rev8 a0, a0
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; RV64ZB-NEXT: srli a0, a0, 48
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; RV64ZB-NEXT: ret
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%1 = call i16 @llvm.bswap.i16(i16 %a)
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%2 = shl i16 %1, 7
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%3 = call i16 @llvm.bswap.i16(i16 %2)
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ret i16 %3
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}
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define i16 @test_bswap_shli_8_bswap_i16(i16 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_8_bswap_i16:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: slli a0, a0, 16
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; RV32ZB-NEXT: srli a0, a0, 24
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_8_bswap_i16:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: slli a0, a0, 48
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; RV64ZB-NEXT: srli a0, a0, 56
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; RV64ZB-NEXT: ret
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%1 = call i16 @llvm.bswap.i16(i16 %a)
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%2 = shl i16 %1, 8
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%3 = call i16 @llvm.bswap.i16(i16 %2)
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ret i16 %3
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}
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define i32 @test_bswap_shli_8_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_8_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: srli a0, a0, 8
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_8_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: srliw a0, a0, 8
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = shl i32 %1, 8
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i32 @test_bswap_shli_16_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_16_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: srli a0, a0, 16
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_16_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: srliw a0, a0, 16
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = shl i32 %1, 16
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i32 @test_bswap_shli_24_bswap_i32(i32 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_24_bswap_i32:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: srli a0, a0, 24
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_24_bswap_i32:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: srliw a0, a0, 24
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; RV64ZB-NEXT: ret
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%1 = call i32 @llvm.bswap.i32(i32 %a)
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%2 = shl i32 %1, 24
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%3 = call i32 @llvm.bswap.i32(i32 %2)
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ret i32 %3
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}
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define i64 @test_bswap_shli_48_bswap_i64(i64 %a) nounwind {
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; RV32ZB-LABEL: test_bswap_shli_48_bswap_i64:
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; RV32ZB: # %bb.0:
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; RV32ZB-NEXT: srli a0, a1, 16
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; RV32ZB-NEXT: li a1, 0
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; RV32ZB-NEXT: ret
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;
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; RV64ZB-LABEL: test_bswap_shli_48_bswap_i64:
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; RV64ZB: # %bb.0:
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; RV64ZB-NEXT: srli a0, a0, 48
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; RV64ZB-NEXT: ret
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%1 = call i64 @llvm.bswap.i64(i64 %a)
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%2 = shl i64 %1, 48
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%3 = call i64 @llvm.bswap.i64(i64 %2)
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ret i64 %3
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}
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