derek.holloway
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82 lines
2.0 KiB
LLVM
82 lines
2.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-- -o - | FileCheck %s
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; This test verifies that we produce different code for different architectures
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; based on target-cpu and target-features attributes.
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; In this case avx has a vmovss instruction and otherwise we should be using movss
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; to materialize constants.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define float @_Z3barv() #0 {
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entry:
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ret float 4.000000e+00
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}
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; CHECK: barv
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; CHECK: vmovss
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define float @_Z4testv() #1 {
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entry:
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ret float 1.000000e+00
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}
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; CHECK: testv
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; CHECK: movss
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define float @_Z3foov() #2 {
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entry:
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ret float 4.000000e+00
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}
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; CHECK: foov
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; CHECK: movss
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define float @_Z3bazv() #0 {
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entry:
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ret float 4.000000e+00
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}
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; CHECK: bazv
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; CHECK: vmovss
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define <2 x i64> @foo(<2 x i64> %a) #3 {
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entry:
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%a.addr = alloca <2 x i64>, align 16
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store <2 x i64> %a, ptr %a.addr, align 16
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%0 = load <2 x i64>, ptr %a.addr, align 16
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%1 = call <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64> %0, i8 4)
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ret <2 x i64> %1
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}
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.x86.aesni.aeskeygenassist(<2 x i64>, i8)
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; CHECK: foo
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; CHECK: aeskeygenassist
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; Function Attrs: nounwind uwtable
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define i32 @bar(i32 %crc, ptr %a) #3 {
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entry:
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%crc.addr = alloca i32, align 4
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%a.addr = alloca ptr, align 8
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store i32 %crc, ptr %crc.addr, align 4
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store ptr %a, ptr %a.addr, align 8
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%0 = load i32, ptr %crc.addr, align 4
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%1 = load ptr, ptr %a.addr, align 8
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%incdec.ptr = getelementptr inbounds i8, ptr %1, i32 1
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store ptr %incdec.ptr, ptr %a.addr, align 8
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%2 = load i8, ptr %1, align 1
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%3 = call i32 @llvm.x86.sse42.crc32.32.8(i32 %0, i8 %2)
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ret i32 %3
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8)
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; CHECK: bar
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; CHECK: crc32b
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attributes #0 = { "target-cpu"="x86-64" "target-features"="+avx2" }
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attributes #1 = { "target-cpu"="x86-64" }
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attributes #2 = { "target-cpu"="corei7" "target-features"="+sse4.2" }
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attributes #3 = { "target-cpu"="x86-64" "target-features"="+avx2,+aes,+crc32" }
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