derek.holloway
7502bf64a4
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314 lines
10 KiB
LLVM
314 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+ssse3 | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; Verify that the following shifts are lowered into a sequence of two shifts plus
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; a blend. On pre-avx2 targets, instead of scalarizing logical and arithmetic
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; packed shift right by a constant build_vector the backend should always try to
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; emit a simpler sequence of two shifts + blend when possible.
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define <8 x i16> @test1(<8 x i16> %a) {
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; SSE-LABEL: test1:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $3, %xmm1
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; SSE-NEXT: psrlw $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test1:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlw $3, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlw $2, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX2-NEXT: retq
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <8 x i16> @test2(<8 x i16> %a) {
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; SSE-LABEL: test2:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrlw $3, %xmm1
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; SSE-NEXT: psrlw $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test2:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test2:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlw $2, %xmm0, %xmm1
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; AVX2-NEXT: vpsrlw $3, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2-NEXT: retq
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%lshr = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <4 x i32> @test3(<4 x i32> %a) {
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; SSE-LABEL: test3:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $3, %xmm1
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrld $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = lshr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <4 x i32> @test4(<4 x i32> %a) {
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; SSE-LABEL: test4:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrld $3, %xmm1
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; SSE-NEXT: psrld $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test4:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrld $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrld $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test4:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <8 x i16> @test5(<8 x i16> %a) {
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; SSE-LABEL: test5:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $3, %xmm1
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; SSE-NEXT: psraw $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test5:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsraw $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsraw $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test5:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsraw $3, %xmm0, %xmm1
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; AVX2-NEXT: vpsraw $2, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; AVX2-NEXT: retq
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <8 x i16> @test6(<8 x i16> %a) {
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; SSE-LABEL: test6:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $3, %xmm1
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; SSE-NEXT: psraw $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test6:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsraw $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsraw $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test6:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsraw $2, %xmm0, %xmm1
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; AVX2-NEXT: vpsraw $3, %xmm0, %xmm0
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2-NEXT: retq
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%lshr = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 2, i16 2, i16 2, i16 2>
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ret <8 x i16> %lshr
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}
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define <4 x i32> @test7(<4 x i32> %a) {
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; SSE-LABEL: test7:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $3, %xmm1
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; SSE-NEXT: psrad $2, %xmm0
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; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test7:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $3, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $2, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test7:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = ashr <4 x i32> %a, <i32 3, i32 2, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <4 x i32> @test8(<4 x i32> %a) {
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; SSE-LABEL: test8:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psrad $3, %xmm1
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; SSE-NEXT: psrad $2, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpsrad $2, %xmm0, %xmm1
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; AVX1-NEXT: vpsrad $3, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: retq
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%lshr = ashr <4 x i32> %a, <i32 3, i32 3, i32 2, i32 2>
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ret <4 x i32> %lshr
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}
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define <8 x i16> @test9(<8 x i16> %a) {
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; SSE-LABEL: test9:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $3, %xmm1
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,65535,65535,65535,0,0,0]
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; SSE-NEXT: psraw $1, %xmm0
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; SSE-NEXT: pand %xmm2, %xmm0
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; SSE-NEXT: pandn %xmm1, %xmm2
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; SSE-NEXT: por %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test9:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsraw $3, %xmm0, %xmm1
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; AVX-NEXT: vpsraw $1, %xmm0, %xmm0
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; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4],xmm1[5,6,7]
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; AVX-NEXT: retq
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%lshr = ashr <8 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3>
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ret <8 x i16> %lshr
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}
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define <8 x i32> @test10(ptr %a) {
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; SSE-LABEL: test10:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa (%rdi), %xmm0
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; SSE-NEXT: psrad $1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test10:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmovdqa (%rdi), %xmm0
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; AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test10:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vmovdqa (%rdi), %ymm0
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; AVX2-NEXT: vpsrad $1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%ld = load <8 x i32>, ptr %a, align 32
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%ashr = ashr <8 x i32> %ld, <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x i32> %ashr
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}
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; test11 vs test12 - show difference between v16i16 that is repeated/non-repeated at v8i16 level (for PBLENDW masks).
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define <16 x i16> @test11(<16 x i16> %a) {
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; SSE-LABEL: test11:
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; SSE: # %bb.0:
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; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [2,8,2,2,2,8,8,8]
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; SSE-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [8,8,8,2,2,2,8,2]
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test11:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
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; AVX1-NEXT: vpsllw $3, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3,4,5],xmm1[6],xmm2[7]
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; AVX1-NEXT: vpsllw $3, %xmm0, %xmm2
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; AVX1-NEXT: vpaddw %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3,4],xmm2[5,6,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test11:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [2,8,2,2,2,8,8,8,8,8,8,2,2,2,8,2]
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; AVX2-NEXT: retq
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%lshr = shl <16 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 1, i16 1, i16 1, i16 3, i16 1>
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ret <16 x i16> %lshr
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}
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define <16 x i16> @test12(<16 x i16> %a) {
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; SSE-LABEL: test12:
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; SSE: # %bb.0:
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; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,8,2,2,2,8,8,8]
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; SSE-NEXT: pmullw %xmm2, %xmm0
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; SSE-NEXT: pmullw %xmm2, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: test12:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
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; AVX1-NEXT: vpsllw $3, %xmm1, %xmm2
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; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4],xmm2[5,6,7]
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; AVX1-NEXT: vpsllw $3, %xmm0, %xmm2
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; AVX1-NEXT: vpaddw %xmm0, %xmm0, %xmm0
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2,3,4],xmm2[5,6,7]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: test12:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpsllw $3, %ymm0, %ymm1
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; AVX2-NEXT: vpaddw %ymm0, %ymm0, %ymm0
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; AVX2-NEXT: vpblendw {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4],ymm1[5,6,7],ymm0[8],ymm1[9],ymm0[10,11,12],ymm1[13,14,15]
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; AVX2-NEXT: retq
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%lshr = shl <16 x i16> %a, <i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3, i16 1, i16 3, i16 1, i16 1, i16 1, i16 3, i16 3, i16 3>
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ret <16 x i16> %lshr
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}
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