derek.holloway
7502bf64a4
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331 lines
9.4 KiB
LLVM
331 lines
9.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=early-cse -earlycse-debug-hash -S < %s | FileCheck %s
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; RUN: opt -passes='early-cse<memssa>' -S < %s | FileCheck %s
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; Most basic case, fully identical PHI nodes
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define void @test0(i32 %v0, i32 %v1, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @test0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0]], [[B0]] ], [ [[V1]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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ret void
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}
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; Fully identical PHI nodes, but order of operands differs
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define void @test1(i32 %v0, i32 %v1, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V1]], [[B1]] ], [ [[V0]], [[B0]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v1, %b1 ], [ %v0, %b0 ]
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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ret void
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}
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; Different incoming values in second PHI
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define void @negative_test2(i32 %v0, i32 %v1, i32 %v2, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @negative_test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0]], [[B0]] ], [ [[V2:%.*]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v2, %b1 ] ; from %b0 takes %v2 instead of %v1
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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ret void
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}
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define void @negative_test3(i32 %v0, i32 %v1, i32 %v2, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @negative_test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V2:%.*]], [[B1]] ], [ [[V0]], [[B0]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v2, %b1 ], [ %v0, %b0 ] ; from %b0 takes %v2 instead of %v1
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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ret void
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}
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define void @negative_test4(i32 %v0, i32 %v1, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @negative_test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V1]], [[B1]] ], [ [[V0]], [[B0]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v1, %b1 ], [ %v0, %b0 ] ; incoming values are swapped
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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ret void
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}
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; Both PHI's are identical, but the first one has no uses, so ignore it.
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define void @test5(i32 %v0, i32 %v1, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ] ; unused
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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store i32 %i1, ptr %d1
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ret void
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}
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; Second PHI has no uses
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define void @test6(i32 %v0, i32 %v1, i1 %c, ptr %d0, ptr %d1) {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ] ; unused
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store i32 %i0, ptr %d0
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ret void
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}
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; Non-matching PHI node should be ignored without terminating CSE.
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define void @test7(i32 %v0, i32 %v1, i16 %v2, i16 %v3, i1 %c, ptr %d0, ptr %d1, ptr %d2) {
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; CHECK-LABEL: @test7(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[IBAD:%.*]] = phi i16 [ [[V2:%.*]], [[B0]] ], [ [[V3:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0]], [[B0]] ], [ [[V1]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: store i16 [[IBAD]], ptr [[D2:%.*]], align 2
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%iBAD = phi i16 [ %v2, %b0 ], [ %v3, %b1 ]
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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store i16 %iBAD, ptr %d2
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ret void
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}
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define void @test8(i32 %v0, i32 %v1, i16 %v2, i16 %v3, i1 %c, ptr %d0, ptr %d1, ptr %d2) {
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; CHECK-LABEL: @test8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[IBAD:%.*]] = phi i16 [ [[V2:%.*]], [[B0]] ], [ [[V3:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0]], [[B0]] ], [ [[V1]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: store i16 [[IBAD]], ptr [[D2:%.*]], align 2
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%iBAD = phi i16 [ %v2, %b0 ], [ %v3, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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store i16 %iBAD, ptr %d2
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ret void
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}
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define void @test9(i32 %v0, i32 %v1, i16 %v2, i16 %v3, i1 %c, ptr %d0, ptr %d1, ptr %d2) {
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; CHECK-LABEL: @test9(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[B0:%.*]], label [[B1:%.*]]
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; CHECK: b0:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: br label [[END]]
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; CHECK: end:
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; CHECK-NEXT: [[I0:%.*]] = phi i32 [ [[V0:%.*]], [[B0]] ], [ [[V1:%.*]], [[B1]] ]
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; CHECK-NEXT: [[I1:%.*]] = phi i32 [ [[V0]], [[B0]] ], [ [[V1]], [[B1]] ]
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; CHECK-NEXT: [[IBAD:%.*]] = phi i16 [ [[V2:%.*]], [[B0]] ], [ [[V3:%.*]], [[B1]] ]
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; CHECK-NEXT: store i32 [[I0]], ptr [[D0:%.*]], align 4
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; CHECK-NEXT: store i32 [[I1]], ptr [[D1:%.*]], align 4
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; CHECK-NEXT: store i16 [[IBAD]], ptr [[D2:%.*]], align 2
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; CHECK-NEXT: ret void
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;
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entry:
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br i1 %c, label %b0, label %b1
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b0:
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br label %end
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b1:
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br label %end
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end:
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%i0 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%i1 = phi i32 [ %v0, %b0 ], [ %v1, %b1 ]
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%iBAD = phi i16 [ %v2, %b0 ], [ %v3, %b1 ]
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store i32 %i0, ptr %d0
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store i32 %i1, ptr %d1
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store i16 %iBAD, ptr %d2
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ret void
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}
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