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TheRock/compiler/amd-llvm/llvm/test/Transforms/LoopVectorize/cast-induction.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

569 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S %s | FileCheck --check-prefix=VF4 %s
; RUN: opt -passes=loop-vectorize -force-vector-interleave=2 -force-vector-width=1 -S %s | FileCheck --check-prefix=IC2 %s
; rdar://problem/12848162
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
@a = common global [2048 x i32] zeroinitializer, align 16
define void @example12() {
; VF4-LABEL: define void @example12() {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: br label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
; VF4-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP0]], align 4
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
; VF4-NEXT: [[TMP1:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; VF4-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
; IC2-LABEL: define void @example12() {
; IC2-NEXT: [[ENTRY:.*:]]
; IC2-NEXT: br label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 1
; IC2-NEXT: [[TMP1:%.*]] = trunc i64 [[INDEX]] to i32
; IC2-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; IC2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
; IC2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP0]]
; IC2-NEXT: store i32 [[TMP1]], ptr [[TMP3]], align 4
; IC2-NEXT: store i32 [[TMP2]], ptr [[TMP4]], align 4
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; IC2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; IC2-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: br label %[[EXIT:.*]]
; IC2: [[EXIT]]:
; IC2-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %iv
%iv.trunc = trunc i64 %iv to i32
store i32 %iv.trunc, ptr %gep, align 4
%iv.next = add i64 %iv, 1
%iv.next.trunc = trunc i64 %iv.next to i32
%exitcond = icmp eq i32 %iv.next.trunc, 1024
br i1 %exitcond, label %exit, label %loop
exit:
ret void
}
define void @redundant_iv_cast(ptr %dst) {
; VF4-LABEL: define void @redundant_iv_cast(
; VF4-SAME: ptr [[DST:%.*]]) {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: br label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16
; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[OFFSET_IDX]]
; VF4-NEXT: store <4 x i16> [[VEC_IND]], ptr [[TMP0]], align 2
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[VEC_IND]], splat (i16 4)
; VF4-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10000
; VF4-NEXT: br i1 [[TMP1]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: br label %[[SCALAR_PH:.*]]
; VF4: [[SCALAR_PH]]:
; VF4-NEXT: br label %[[LOOP:.*]]
; VF4: [[LOOP]]:
; VF4-NEXT: [[J_0:%.*]] = phi i16 [ 10000, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[LOOP]] ]
; VF4-NEXT: [[EXT:%.*]] = zext i16 [[J_0]] to i32
; VF4-NEXT: [[TRUNC:%.*]] = trunc i32 [[EXT]] to i16
; VF4-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[J_0]]
; VF4-NEXT: store i16 [[TRUNC]], ptr [[GEP]], align 2
; VF4-NEXT: [[TMP2:%.*]] = icmp eq i16 10000, [[J_0]]
; VF4-NEXT: [[INC]] = add i16 [[J_0]], 1
; VF4-NEXT: br i1 [[TMP2]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
; IC2-LABEL: define void @redundant_iv_cast(
; IC2-SAME: ptr [[DST:%.*]]) {
; IC2-NEXT: [[ENTRY:.*:]]
; IC2-NEXT: br label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i16
; IC2-NEXT: [[TMP0:%.*]] = add i16 [[OFFSET_IDX]], 1
; IC2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[OFFSET_IDX]]
; IC2-NEXT: [[TMP2:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[TMP0]]
; IC2-NEXT: store i16 [[OFFSET_IDX]], ptr [[TMP1]], align 2
; IC2-NEXT: store i16 [[TMP0]], ptr [[TMP2]], align 2
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; IC2-NEXT: [[TMP3:%.*]] = icmp eq i32 [[INDEX_NEXT]], 10000
; IC2-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: br label %[[SCALAR_PH:.*]]
; IC2: [[SCALAR_PH]]:
; IC2-NEXT: br label %[[LOOP:.*]]
; IC2: [[LOOP]]:
; IC2-NEXT: [[J_0:%.*]] = phi i16 [ 10000, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[LOOP]] ]
; IC2-NEXT: [[EXT:%.*]] = zext i16 [[J_0]] to i32
; IC2-NEXT: [[TRUNC:%.*]] = trunc i32 [[EXT]] to i16
; IC2-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i16 [[J_0]]
; IC2-NEXT: store i16 [[TRUNC]], ptr [[GEP]], align 2
; IC2-NEXT: [[TMP4:%.*]] = icmp eq i16 10000, [[J_0]]
; IC2-NEXT: [[INC]] = add i16 [[J_0]], 1
; IC2-NEXT: br i1 [[TMP4]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
; IC2: [[EXIT]]:
; IC2-NEXT: ret void
;
entry:
br label %loop
loop:
%j.0 = phi i16 [ 0, %entry ], [ %inc, %loop ]
%ext = zext i16 %j.0 to i32
%trunc = trunc i32 %ext to i16
%gep = getelementptr inbounds i16, ptr %dst, i16 %j.0
store i16 %trunc, ptr %gep
%0 = icmp eq i16 10000, %j.0
%inc = add i16 %j.0, 1
br i1 %0, label %exit, label %loop
exit:
ret void
}
define void @cast_variable_step(i64 %step) {
; VF4-LABEL: define void @cast_variable_step(
; VF4-SAME: i64 [[STEP:%.*]]) {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: br label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: [[TMP0:%.*]] = trunc i64 [[STEP]] to i32
; VF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
; VF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
; VF4-NEXT: [[TMP1:%.*]] = mul <4 x i32> <i32 0, i32 1, i32 2, i32 3>, [[BROADCAST_SPLAT]]
; VF4-NEXT: [[INDUCTION:%.*]] = add <4 x i32> splat (i32 10), [[TMP1]]
; VF4-NEXT: [[TMP2:%.*]] = shl i32 [[TMP0]], 2
; VF4-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i64 0
; VF4-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT1]], <4 x i32> poison, <4 x i32> zeroinitializer
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
; VF4-NEXT: store <4 x i32> [[VEC_IND]], ptr [[TMP3]], align 4
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT2]]
; VF4-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; VF4-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
; IC2-LABEL: define void @cast_variable_step(
; IC2-SAME: i64 [[STEP:%.*]]) {
; IC2-NEXT: [[ENTRY:.*:]]
; IC2-NEXT: br label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: [[TMP0:%.*]] = trunc i64 [[STEP]] to i32
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
; IC2-NEXT: [[TMP2:%.*]] = mul i64 [[INDEX]], [[STEP]]
; IC2-NEXT: [[OFFSET_IDX:%.*]] = add i64 10, [[TMP2]]
; IC2-NEXT: [[TMP3:%.*]] = trunc i64 [[OFFSET_IDX]] to i32
; IC2-NEXT: [[TMP4:%.*]] = mul i32 1, [[TMP0]]
; IC2-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], [[TMP4]]
; IC2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[INDEX]]
; IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 [[TMP1]]
; IC2-NEXT: store i32 [[TMP3]], ptr [[TMP6]], align 4
; IC2-NEXT: store i32 [[TMP5]], ptr [[TMP7]], align 4
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; IC2-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; IC2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: br label %[[EXIT:.*]]
; IC2: [[EXIT]]:
; IC2-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%iv.1 = phi i64 [ 10, %entry ], [ %iv.1.next, %loop ]
%gep = getelementptr inbounds [2048 x i32], ptr @a, i64 0, i64 %iv
%iv.1.trunc = trunc i64 %iv.1 to i32
store i32 %iv.1.trunc, ptr %gep, align 4
%iv.next = add i64 %iv, 1
%iv.1.next = add i64 %iv.1, %step
%exitcond = icmp eq i64 %iv.next, 1024
br i1 %exitcond, label %exit, label %loop
exit:
ret void
}
define void @cast_induction_tail_folding(ptr %A) {
; VF4-LABEL: define void @cast_induction_tail_folding(
; VF4-SAME: ptr [[A:%.*]]) {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: br label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
; VF4: [[PRED_STORE_IF]]:
; VF4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 0
; VF4-NEXT: store i32 0, ptr [[TMP0]], align 4
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE]]
; VF4: [[PRED_STORE_CONTINUE]]:
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2:.*]]
; VF4: [[PRED_STORE_IF1]]:
; VF4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 1
; VF4-NEXT: store i32 1, ptr [[TMP1]], align 4
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE2]]
; VF4: [[PRED_STORE_CONTINUE2]]:
; VF4-NEXT: br i1 true, label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4:.*]]
; VF4: [[PRED_STORE_IF3]]:
; VF4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 2
; VF4-NEXT: store i32 2, ptr [[TMP2]], align 4
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE4]]
; VF4: [[PRED_STORE_CONTINUE4]]:
; VF4-NEXT: br i1 false, label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6:.*]]
; VF4: [[PRED_STORE_IF5]]:
; VF4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 3
; VF4-NEXT: store i32 3, ptr [[TMP3]], align 4
; VF4-NEXT: br label %[[PRED_STORE_CONTINUE6]]
; VF4: [[PRED_STORE_CONTINUE6]]:
; VF4-NEXT: br label %[[MIDDLE_BLOCK:.*]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: br label %[[EXIT:.*]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
; IC2-LABEL: define void @cast_induction_tail_folding(
; IC2-SAME: ptr [[A:%.*]]) {
; IC2-NEXT: [[ENTRY:.*:]]
; IC2-NEXT: br label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE2:.*]] ]
; IC2-NEXT: [[INDEX1:%.*]] = add i32 [[INDEX]], 1
; IC2-NEXT: [[TMP2:%.*]] = icmp ule i32 [[INDEX]], 2
; IC2-NEXT: [[TMP3:%.*]] = icmp ule i32 [[INDEX1]], 2
; IC2-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
; IC2: [[PRED_STORE_IF]]:
; IC2-NEXT: [[TMP4:%.*]] = sext i32 [[INDEX]] to i64
; IC2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]]
; IC2-NEXT: store i32 [[INDEX]], ptr [[TMP5]], align 4
; IC2-NEXT: br label %[[PRED_STORE_CONTINUE]]
; IC2: [[PRED_STORE_CONTINUE]]:
; IC2-NEXT: br i1 [[TMP3]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2]]
; IC2: [[PRED_STORE_IF1]]:
; IC2-NEXT: [[TMP6:%.*]] = sext i32 [[INDEX1]] to i64
; IC2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]]
; IC2-NEXT: store i32 [[INDEX1]], ptr [[TMP7]], align 4
; IC2-NEXT: br label %[[PRED_STORE_CONTINUE2]]
; IC2: [[PRED_STORE_CONTINUE2]]:
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; IC2-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
; IC2-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: br label %[[EXIT:.*]]
; IC2: [[EXIT]]:
; IC2-NEXT: ret void
;
entry:
br label %loop
loop:
%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
%iv.ext = sext i32 %iv to i64
%iv.trunc = trunc i64 %iv.ext to i32
%gep = getelementptr inbounds i32, ptr %A, i64 %iv.ext
store i32 %iv.trunc, ptr %gep
%iv.next = add i32 %iv, 1
%c = icmp slt i32 %iv.next, 3
br i1 %c, label %loop, label %exit
exit:
ret void
}
define void @test_start_zext(i32 %start, ptr %dst) {
; VF4-LABEL: define void @test_start_zext(
; VF4-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
; VF4-NEXT: [[ENTRY:.*:]]
; VF4-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64
; VF4-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]]
; VF4-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; VF4: [[VECTOR_SCEVCHECK]]:
; VF4-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[START]], 1
; VF4-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[DST]], i64 [[INDEX]]
; VF4-NEXT: store <4 x float> zeroinitializer, ptr [[TMP1]], align 4
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; VF4-NEXT: [[TMP2:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
; VF4-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: br label %[[SCALAR_PH]]
; VF4: [[SCALAR_PH]]:
; VF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 97, %[[MIDDLE_BLOCK]] ], [ [[START_EXT]], %[[VECTOR_SCEVCHECK]] ]
; VF4-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 96, %[[MIDDLE_BLOCK]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; VF4-NEXT: br label %[[LOOP:.*]]
; VF4: [[LOOP]]:
; VF4-NEXT: [[IV_0:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP]] ]
; VF4-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]
; VF4-NEXT: [[GEP_DST:%.*]] = getelementptr float, ptr [[DST]], i64 [[IV_1]]
; VF4-NEXT: store float 0.000000e+00, ptr [[GEP_DST]], align 4
; VF4-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], [[START_EXT]]
; VF4-NEXT: [[IV_0_NEXT]] = add i64 [[IV_0]], 1
; VF4-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_0_NEXT]], 100
; VF4-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
; VF4: [[EXIT]]:
; VF4-NEXT: ret void
;
; IC2-LABEL: define void @test_start_zext(
; IC2-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
; IC2-NEXT: [[ENTRY:.*]]:
; IC2-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64
; IC2-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
; IC2-NEXT: [[TMP1:%.*]] = add i64 [[START_EXT]], [[N_VEC]]
; IC2-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], [[START_EXT]]
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[START_EXT]]
; IC2-NEXT: [[TMP3:%.*]] = mul i64 1, [[START_EXT]]
; IC2-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], [[TMP3]]
; IC2-NEXT: [[TMP5:%.*]] = getelementptr float, ptr [[DST]], i64 [[OFFSET_IDX]]
; IC2-NEXT: [[TMP6:%.*]] = getelementptr float, ptr [[DST]], i64 [[TMP4]]
; IC2-NEXT: store float 0.000000e+00, ptr [[TMP5]], align 4
; IC2-NEXT: store float 0.000000e+00, ptr [[TMP6]], align 4
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; IC2-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; IC2-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
; IC2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC2: [[SCALAR_PH]]:
; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[START_EXT]], %[[ENTRY]] ]
; IC2-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
; IC2-NEXT: br label %[[LOOP:.*]]
; IC2: [[LOOP]]:
; IC2-NEXT: [[IV_0:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_0_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT: [[GEP_DST:%.*]] = getelementptr float, ptr [[DST]], i64 [[IV_1]]
; IC2-NEXT: store float 0.000000e+00, ptr [[GEP_DST]], align 4
; IC2-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], [[START_EXT]]
; IC2-NEXT: [[IV_0_NEXT]] = add i64 [[IV_0]], 1
; IC2-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_0_NEXT]], 100
; IC2-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP8:![0-9]+]]
; IC2: [[EXIT]]:
; IC2-NEXT: ret void
;
entry:
%start.ext = zext i32 %start to i64
br label %loop
loop:
%iv.0 = phi i64 [ %start.ext, %entry ], [ %iv.0.next, %loop ]
%iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ]
%gep.dst = getelementptr float, ptr %dst, i64 %iv.1
store float 0.0, ptr %gep.dst, align 4
%iv.1.next = add i64 %iv.1, %start.ext
%iv.0.next = add i64 %iv.0, 1
%ec = icmp eq i64 %iv.0.next, 100
br i1 %ec, label %exit, label %loop
exit:
ret void
}
define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; VF4-LABEL: define i64 @induction_cast_chain_cleared_by_dce(
; VF4-SAME: i64 [[N:%.*]], i64 [[MASK_INIT:%.*]]) {
; VF4-NEXT: [[ENTRY:.*]]:
; VF4-NEXT: [[MASK:%.*]] = and i64 [[MASK_INIT]], -4294967296
; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; VF4-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; VF4-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; VF4-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
; VF4-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[MASK]]
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4
; VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF4: [[VECTOR_SCEVCHECK]]:
; VF4-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[MASK]], 2
; VF4-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP4]])
; VF4-NEXT: [[TMP5:%.*]] = add i64 [[SMAX]], -2
; VF4-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], [[MASK]]
; VF4-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
; VF4-NEXT: [[TMP8:%.*]] = add i32 1, [[TMP7]]
; VF4-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 1
; VF4-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP6]], 4294967295
; VF4-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
; VF4-NEXT: [[TMP12:%.*]] = add nuw nsw i64 [[MASK]], 1
; VF4-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP12]], 1
; VF4-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[IDENT_CHECK]]
; VF4-NEXT: br i1 [[TMP13]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; VF4: [[VECTOR_PH]]:
; VF4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4
; VF4-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
; VF4-NEXT: [[TMP14:%.*]] = mul i64 [[N_VEC]], [[TMP3]]
; VF4-NEXT: [[TMP15:%.*]] = add i64 1, [[TMP14]]
; VF4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[TMP3]], i64 0
; VF4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
; VF4-NEXT: [[TMP16:%.*]] = mul <4 x i64> <i64 0, i64 1, i64 2, i64 3>, [[BROADCAST_SPLAT]]
; VF4-NEXT: [[INDUCTION:%.*]] = add <4 x i64> splat (i64 1), [[TMP16]]
; VF4-NEXT: [[TMP17:%.*]] = shl i64 [[TMP3]], 2
; VF4-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TMP17]], i64 0
; VF4-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer
; VF4-NEXT: br label %[[VECTOR_BODY:.*]]
; VF4: [[VECTOR_BODY]]:
; VF4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
; VF4-NEXT: [[TMP18]] = add <4 x i64> [[VEC_PHI]], [[VEC_IND]]
; VF4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; VF4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT3]]
; VF4-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; VF4-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
; VF4: [[MIDDLE_BLOCK]]:
; VF4-NEXT: [[TMP20:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP18]])
; VF4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
; VF4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; VF4: [[SCALAR_PH]]:
; VF4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ 1, %[[ENTRY]] ], [ 1, %[[VECTOR_SCEVCHECK]] ]
; VF4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; VF4-NEXT: br label %[[LOOP:.*]]
; VF4: [[LOOP]]:
; VF4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; VF4-NEXT: [[ACC:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ACC_NEXT:%.*]], %[[LOOP]] ]
; VF4-NEXT: [[LO:%.*]] = and i64 [[IV]], 4294967295
; VF4-NEXT: [[COMBINED:%.*]] = or disjoint i64 [[MASK]], [[LO]]
; VF4-NEXT: [[ACC_NEXT]] = add i64 [[ACC]], [[IV]]
; VF4-NEXT: [[IV_NEXT]] = add i64 [[COMBINED]], 1
; VF4-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV_NEXT]], [[N]]
; VF4-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP9:![0-9]+]]
; VF4: [[EXIT]]:
; VF4-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i64 [ [[ACC_NEXT]], %[[LOOP]] ], [ [[TMP20]], %[[MIDDLE_BLOCK]] ]
; VF4-NEXT: ret i64 [[ACC_NEXT_LCSSA]]
;
; IC2-LABEL: define i64 @induction_cast_chain_cleared_by_dce(
; IC2-SAME: i64 [[N:%.*]], i64 [[MASK_INIT:%.*]]) {
; IC2-NEXT: [[ENTRY:.*]]:
; IC2-NEXT: [[MASK:%.*]] = and i64 [[MASK_INIT]], -4294967296
; IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; IC2-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; IC2-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; IC2-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
; IC2-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[MASK]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; IC2: [[VECTOR_SCEVCHECK]]:
; IC2-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[MASK]], 2
; IC2-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP4]])
; IC2-NEXT: [[TMP5:%.*]] = add i64 [[SMAX]], -2
; IC2-NEXT: [[TMP6:%.*]] = sub i64 [[TMP5]], [[MASK]]
; IC2-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
; IC2-NEXT: [[TMP8:%.*]] = add i32 1, [[TMP7]]
; IC2-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 1
; IC2-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP6]], 4294967295
; IC2-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
; IC2-NEXT: [[TMP12:%.*]] = add nuw nsw i64 [[MASK]], 1
; IC2-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP12]], 1
; IC2-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[IDENT_CHECK]]
; IC2-NEXT: br i1 [[TMP13]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
; IC2-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 2
; IC2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]]
; IC2-NEXT: [[TMP14:%.*]] = mul i64 [[N_VEC]], [[TMP3]]
; IC2-NEXT: [[TMP15:%.*]] = add i64 1, [[TMP14]]
; IC2-NEXT: br label %[[VECTOR_BODY:.*]]
; IC2: [[VECTOR_BODY]]:
; IC2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[VEC_PHI:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ]
; IC2-NEXT: [[TMP16:%.*]] = mul i64 [[INDEX]], [[TMP3]]
; IC2-NEXT: [[TMP17:%.*]] = add i64 1, [[TMP16]]
; IC2-NEXT: [[TMP18:%.*]] = mul i64 1, [[TMP3]]
; IC2-NEXT: [[TMP19:%.*]] = add i64 [[TMP17]], [[TMP18]]
; IC2-NEXT: [[TMP20]] = add i64 [[VEC_PHI]], [[TMP17]]
; IC2-NEXT: [[TMP21]] = add i64 [[VEC_PHI2]], [[TMP19]]
; IC2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
; IC2-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; IC2-NEXT: br i1 [[TMP22]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; IC2: [[MIDDLE_BLOCK]]:
; IC2-NEXT: [[BIN_RDX:%.*]] = add i64 [[TMP21]], [[TMP20]]
; IC2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]]
; IC2-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; IC2: [[SCALAR_PH]]:
; IC2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP15]], %[[MIDDLE_BLOCK]] ], [ 1, %[[ENTRY]] ], [ 1, %[[VECTOR_SCEVCHECK]] ]
; IC2-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
; IC2-NEXT: br label %[[LOOP:.*]]
; IC2: [[LOOP]]:
; IC2-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT: [[ACC:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ACC_NEXT:%.*]], %[[LOOP]] ]
; IC2-NEXT: [[LO:%.*]] = and i64 [[IV]], 4294967295
; IC2-NEXT: [[COMBINED:%.*]] = or disjoint i64 [[MASK]], [[LO]]
; IC2-NEXT: [[ACC_NEXT]] = add i64 [[ACC]], [[IV]]
; IC2-NEXT: [[IV_NEXT]] = add i64 [[COMBINED]], 1
; IC2-NEXT: [[CMP:%.*]] = icmp slt i64 [[IV_NEXT]], [[N]]
; IC2-NEXT: br i1 [[CMP]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP10:![0-9]+]]
; IC2: [[EXIT]]:
; IC2-NEXT: [[ACC_NEXT_LCSSA:%.*]] = phi i64 [ [[ACC_NEXT]], %[[LOOP]] ], [ [[BIN_RDX]], %[[MIDDLE_BLOCK]] ]
; IC2-NEXT: ret i64 [[ACC_NEXT_LCSSA]]
;
entry:
%mask = and i64 %mask.init, -4294967296
br label %loop
loop:
%iv = phi i64 [ 1, %entry ], [ %iv.next, %loop ]
%acc = phi i64 [ 0, %entry ], [ %acc.next, %loop ]
%lo = and i64 %iv, 4294967295
%combined = or disjoint i64 %mask, %lo
%acc.next = add i64 %acc, %iv
%iv.next = add i64 %combined, 1
%cmp = icmp slt i64 %iv.next, %n
br i1 %cmp, label %loop, label %exit
exit:
ret i64 %acc.next
}
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