derek.holloway
7502bf64a4
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199 lines
6.7 KiB
MLIR
199 lines
6.7 KiB
MLIR
// RUN: mlir-opt -test-last-modified %s 2>&1 | FileCheck %s
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// Test that RegionBranchOpInterface implementations for OpenACC single-region
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// ops behave reasonably under LastModifiedAnalysis.
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// CHECK-LABEL: test_tag: acc_parallel_after:
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// CHECK: operand #0
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// CHECK-NEXT: - parallel_region
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// CHECK-LABEL: test_tag: acc_parallel_return:
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// CHECK: operand #0
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// CHECK-NEXT: - parallel_region
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func.func @last_mod_openacc_parallel(%arg0: memref<f32>) -> memref<f32> {
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%one = arith.constant 1.0 : f32
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// The only store to %arg0 happens inside the acc.parallel region.
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acc.parallel {
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memref.store %one, %arg0[] {tag_name = "parallel_region"} : memref<f32>
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acc.yield
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}
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// With RegionBranchOpInterface wired up, the last modification at this load
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// is the store inside the acc.parallel region.
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memref.load %arg0[] {tag = "acc_parallel_after"} : memref<f32>
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// And the same store should be seen at the function return.
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return {tag = "acc_parallel_return"} %arg0 : memref<f32>
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}
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// -----
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// CHECK-LABEL: test_tag: acc_serial_after:
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// CHECK: operand #0
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// CHECK-NEXT: - serial_region
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// CHECK-LABEL: test_tag: acc_serial_return:
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// CHECK: operand #0
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// CHECK-NEXT: - serial_region
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func.func @last_mod_openacc_serial(%arg0: memref<f32>) -> memref<f32> {
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%one = arith.constant 1.0 : f32
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// The only store to %arg0 happens inside the acc.serial region.
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acc.serial {
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memref.store %one, %arg0[] {tag_name = "serial_region"} : memref<f32>
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acc.yield
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}
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memref.load %arg0[] {tag = "acc_serial_after"} : memref<f32>
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return {tag = "acc_serial_return"} %arg0 : memref<f32>
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}
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// -----
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// CHECK-LABEL: test_tag: acc_kernels_before:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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// CHECK-LABEL: test_tag: acc_kernels_after:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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func.func @last_mod_openacc_kernels(%arg0: memref<f32>) -> memref<f32> {
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%zero = arith.constant 0.0 : f32
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memref.store %zero, %arg0[] {tag_name = "pre"} : memref<f32>
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memref.load %arg0[] {tag = "acc_kernels_before"} : memref<f32>
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acc.kernels {
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acc.terminator
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}
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memref.load %arg0[] {tag = "acc_kernels_after"} : memref<f32>
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return %arg0 : memref<f32>
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}
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// -----
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// CHECK-LABEL: test_tag: acc_data_before:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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// CHECK-LABEL: test_tag: acc_data_after:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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func.func @last_mod_openacc_data(%arg0: memref<f32>, %mapped: memref<f32>) -> memref<f32> {
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%zero = arith.constant 0.0 : f32
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memref.store %zero, %arg0[] {tag_name = "pre"} : memref<f32>
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memref.load %arg0[] {tag = "acc_data_before"} : memref<f32>
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acc.data {
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acc.terminator
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} attributes {defaultAttr = #acc<defaultvalue none>}
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memref.load %arg0[] {tag = "acc_data_after"} : memref<f32>
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return %arg0 : memref<f32>
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}
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// -----
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// CHECK-LABEL: test_tag: acc_host_before:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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// CHECK-LABEL: test_tag: acc_host_after:
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// CHECK: operand #0
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// CHECK-NEXT: - <unknown>
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func.func @last_mod_openacc_host_data(%arg0: memref<f32>, %mapped: memref<f32>) -> memref<f32> {
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%zero = arith.constant 0.0 : f32
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memref.store %zero, %arg0[] {tag_name = "pre"} : memref<f32>
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memref.load %arg0[] {tag = "acc_host_before"} : memref<f32>
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%devptr = acc.use_device varPtr(%mapped : memref<f32>) varType(tensor<f32>) -> memref<f32>
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acc.host_data dataOperands(%devptr : memref<f32>) {
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acc.terminator
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}
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memref.load %arg0[] {tag = "acc_host_after"} : memref<f32>
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return %arg0 : memref<f32>
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}
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// -----
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// structured acc.loop: the RegionBranch is modeled
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// as scf.for with a backedge to the parent op.
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// CHECK-LABEL: test_tag: acc_loop_before:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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// CHECK-LABEL: test_tag: acc_loop_inside:
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// CHECK: operand #0
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// CHECK-NEXT: - loop_region
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// CHECK-LABEL: test_tag: acc_loop_after:
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// CHECK: operand #0
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// CHECK-DAG: - pre
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// CHECK-DAG: - loop_region
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// the last writer is either the pre-loop store or
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// the store in the loop depending on the iteration count
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// CHECK-LABEL: test_tag: acc_loop_post:
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// CHECK: operand #0
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// CHECK-NEXT: - post_loop
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// CHECK-LABEL: test_tag: acc_loop_return:
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// CHECK: operand #0
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// CHECK-NEXT: - post_loop
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func.func @last_mod_openacc_loop(%arg0: memref<f32>) -> memref<f32> {
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%zero = arith.constant 0.0 : f32
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memref.store %zero, %arg0[] {tag_name = "pre"} : memref<f32>
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memref.load %arg0[] {tag = "acc_loop_before"} : memref<f32>
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%one = arith.constant 1.0 : f32
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%c1_i32 = arith.constant 1 : i32
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%c10_i32 = arith.constant 10 : i32
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acc.loop control(%iv : i32) = (%c1_i32 : i32) to (%c10_i32 : i32)
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step (%c1_i32 : i32) {
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memref.store %one, %arg0[] {tag_name = "loop_region"} : memref<f32>
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memref.load %arg0[] {tag = "acc_loop_inside"} : memref<f32>
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acc.yield
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} attributes {auto_ = [#acc.device_type<none>]}
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memref.load %arg0[] {tag = "acc_loop_after"} : memref<f32>
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memref.store %zero, %arg0[] {tag_name = "post_loop"} : memref<f32>
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memref.load %arg0[] {tag = "acc_loop_post"} : memref<f32>
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return {tag = "acc_loop_return"} %arg0 : memref<f32>
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}
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// -----
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// Unstructured acc.loop: the RegionBranch is modeled with explicit CFG and early
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// exits, and the RegionBranch graph only exposes a single entry and single
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// exit edge (no region backedge).
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//
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// CHECK-LABEL: test_tag: acc_loop_unstructured_before:
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// CHECK: operand #0
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// CHECK-NEXT: - pre
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// CHECK-LABEL: test_tag: acc_loop_unstructured_after:
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// CHECK: operand #0
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// CHECK-DAG: - loop_unstructured_early
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// CHECK-DAG: - loop_unstructured_normal
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// the last writer can be either of the two stores in the loop
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func.func @last_mod_openacc_loop_unstructured(%arg0: memref<f32>) -> memref<f32> {
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%zero = arith.constant 0.0 : f32
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%one = arith.constant 1.0 : f32
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memref.store %zero, %arg0[] {tag_name = "pre"} : memref<f32>
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memref.load %arg0[] {tag = "acc_loop_unstructured_before"} : memref<f32>
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%c0_i32 = arith.constant 0 : i32
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%c1_i32 = arith.constant 1 : i32
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%c5_i32 = arith.constant 5 : i32
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acc.loop {
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^entry:
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cf.br ^header(%c0_i32 : i32)
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^header(%iv: i32):
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%is_early = arith.cmpi eq, %iv, %c1_i32 : i32
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cf.cond_br %is_early, ^early_exit, ^cont
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^cont:
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// Normal loop increment and exit when iv reaches 5.
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%iv_next = arith.addi %iv, %c1_i32 : i32
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%is_done = arith.cmpi eq, %iv_next, %c5_i32 : i32
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cf.cond_br %is_done, ^normal_exit, ^header(%iv_next : i32)
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^early_exit:
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memref.store %one, %arg0[] {tag_name = "loop_unstructured_early"} : memref<f32>
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acc.yield
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^normal_exit:
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memref.store %one, %arg0[] {tag_name = "loop_unstructured_normal"} : memref<f32>
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acc.yield
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} attributes {auto_ = [#acc.device_type<none>], unstructured}
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memref.load %arg0[] {tag = "acc_loop_unstructured_after"} : memref<f32>
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return %arg0 : memref<f32>
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}
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