derek.holloway
7502bf64a4
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193 lines
13 KiB
Plaintext
193 lines
13 KiB
Plaintext
; REQUIRES: spirv-as
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; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
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; RUN: spirv-val %t.spv
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; RUN: llvm-spirv %t.spv -r --spirv-target-env=SPV-IR -o %t.rev.bc
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; RUN: llvm-dis %t.rev.bc -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SPV-IR
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; RUN: llvm-spirv %t.rev.bc -o - -spirv-text | FileCheck %s --check-prefix=CHECK-SPV-BACK
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; RUN: llvm-spirv %t.spv -r --spirv-target-env=CL2.0 -o - | llvm-dis | FileCheck %s --check-prefixes=CHECK,CHECK-CL20
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; CHECK-SPV-BACK: ExtInstImport [[Set:[0-9]+]] "OpenCL.std"
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; CHECK-SPV-BACK: TypeInt [[Int32:[0-9]+]] 32
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; CHECK-SPV-BACK: Constant [[Int32]] [[Zero:[0-9]+]] 0
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; CHECK-SPV-BACK: TypeVoid [[VoidTy:[0-9]+]]
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; CHECK-LABEL: spir_kernel void @test
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; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-SPV-IR: call spir_func void @_Z24__spirv_ocl_vstore_halfnDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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;
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn
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; CHECK-CL20: call spir_func void @_Z12vstore_half2Dv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z12vstore_half3Dv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z12vstore_half4Dv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z12vstore_half8Dv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z13vstore_half16Dv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-LABEL: spir_kernel void @testRTE
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 0)
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;
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 0
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; CHECK-CL20: call spir_func void @_Z16vstore_half2_rteDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half3_rteDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half4_rteDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half8_rteDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z17vstore_half16_rteDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-LABEL: spir_kernel void @testRTZ
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 1)
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;
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 1
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; CHECK-CL20: call spir_func void @_Z16vstore_half2_rtzDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half3_rtzDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half4_rtzDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half8_rtzDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z17vstore_half16_rtzDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-LABEL: spir_kernel void @testRTP
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 2)
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;
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 2
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; CHECK-CL20: call spir_func void @_Z16vstore_half2_rtpDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half3_rtpDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half4_rtpDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half8_rtpDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z17vstore_half16_rtpDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-LABEL: spir_kernel void @testRTN
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv2_fjPU3AS1Dhi(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv3_fjPU3AS1Dhi(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv4_fjPU3AS1Dhi(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv8_fjPU3AS1Dhi(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
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; CHECK-SPV-IR: call spir_func void @_Z26__spirv_ocl_vstore_halfn_rDv16_fjPU3AS1Dhi(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}}, i32 3)
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;
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
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; CHECK-SPV-BACK: ExtInst [[VoidTy]] {{.*}} [[Set]] vstore_halfn_r {{.*}} [[Zero]] {{.*}} 3
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; CHECK-CL20: call spir_func void @_Z16vstore_half2_rtnDv2_fjPU3AS1Dh(<2 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half3_rtnDv3_fjPU3AS1Dh(<3 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half4_rtnDv4_fjPU3AS1Dh(<4 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z16vstore_half8_rtnDv8_fjPU3AS1Dh(<8 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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; CHECK-CL20: call spir_func void @_Z17vstore_half16_rtnDv16_fjPU3AS1Dh(<16 x float> {{.*}}, i32 0, ptr addrspace(1) {{.*}})
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OpCapability Addresses
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OpCapability Kernel
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OpCapability Vector16
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OpCapability Float16Buffer
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%1 = OpExtInstImport "OpenCL.std"
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OpMemoryModel Physical32 OpenCL
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OpEntryPoint Kernel %6 "test"
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OpEntryPoint Kernel %27 "testRTE"
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OpEntryPoint Kernel %35 "testRTZ"
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OpEntryPoint Kernel %43 "testRTP"
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OpEntryPoint Kernel %51 "testRTN"
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%59 = OpString "kernel_arg_type.test.half*,"
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%60 = OpString "kernel_arg_type.testRTE.half*,"
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%61 = OpString "kernel_arg_type.testRTZ.half*,"
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%62 = OpString "kernel_arg_type.testRTP.half*,"
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%63 = OpString "kernel_arg_type.testRTN.half*,"
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OpSource OpenCL_C 200000
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%uint = OpTypeInt 32 0
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%uint_0 = OpConstant %uint 0
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%void = OpTypeVoid
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%half = OpTypeFloat 16
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%_ptr_CrossWorkgroup_half = OpTypePointer CrossWorkgroup %half
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%5 = OpTypeFunction %void %_ptr_CrossWorkgroup_half
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%float = OpTypeFloat 32
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%v2float = OpTypeVector %float 2
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%v3float = OpTypeVector %float 3
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%v4float = OpTypeVector %float 4
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%v8float = OpTypeVector %float 8
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%v16float = OpTypeVector %float 16
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%11 = OpConstantNull %v2float
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%16 = OpConstantNull %v3float
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%19 = OpConstantNull %v4float
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%22 = OpConstantNull %v8float
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%25 = OpConstantNull %v16float
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%6 = OpFunction %void None %5
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%ptr = OpFunctionParameter %_ptr_CrossWorkgroup_half
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%entry = OpLabel
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%14 = OpExtInst %void %1 vstore_halfn %11 %uint_0 %ptr
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%17 = OpExtInst %void %1 vstore_halfn %16 %uint_0 %ptr
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%20 = OpExtInst %void %1 vstore_halfn %19 %uint_0 %ptr
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%23 = OpExtInst %void %1 vstore_halfn %22 %uint_0 %ptr
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%26 = OpExtInst %void %1 vstore_halfn %25 %uint_0 %ptr
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OpReturn
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OpFunctionEnd
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%27 = OpFunction %void None %5
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%ptr_0 = OpFunctionParameter %_ptr_CrossWorkgroup_half
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%entry_0 = OpLabel
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%30 = OpExtInst %void %1 vstore_halfn_r %11 %uint_0 %ptr_0 RTE
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%31 = OpExtInst %void %1 vstore_halfn_r %16 %uint_0 %ptr_0 RTE
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%32 = OpExtInst %void %1 vstore_halfn_r %19 %uint_0 %ptr_0 RTE
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%33 = OpExtInst %void %1 vstore_halfn_r %22 %uint_0 %ptr_0 RTE
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%34 = OpExtInst %void %1 vstore_halfn_r %25 %uint_0 %ptr_0 RTE
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OpReturn
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OpFunctionEnd
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%35 = OpFunction %void None %5
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%ptr_1 = OpFunctionParameter %_ptr_CrossWorkgroup_half
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%entry_1 = OpLabel
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%38 = OpExtInst %void %1 vstore_halfn_r %11 %uint_0 %ptr_1 RTZ
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%39 = OpExtInst %void %1 vstore_halfn_r %16 %uint_0 %ptr_1 RTZ
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%40 = OpExtInst %void %1 vstore_halfn_r %19 %uint_0 %ptr_1 RTZ
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%41 = OpExtInst %void %1 vstore_halfn_r %22 %uint_0 %ptr_1 RTZ
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%42 = OpExtInst %void %1 vstore_halfn_r %25 %uint_0 %ptr_1 RTZ
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OpReturn
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OpFunctionEnd
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%43 = OpFunction %void None %5
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%ptr_2 = OpFunctionParameter %_ptr_CrossWorkgroup_half
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%entry_2 = OpLabel
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%46 = OpExtInst %void %1 vstore_halfn_r %11 %uint_0 %ptr_2 RTP
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%47 = OpExtInst %void %1 vstore_halfn_r %16 %uint_0 %ptr_2 RTP
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%48 = OpExtInst %void %1 vstore_halfn_r %19 %uint_0 %ptr_2 RTP
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%49 = OpExtInst %void %1 vstore_halfn_r %22 %uint_0 %ptr_2 RTP
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%50 = OpExtInst %void %1 vstore_halfn_r %25 %uint_0 %ptr_2 RTP
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OpReturn
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OpFunctionEnd
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%51 = OpFunction %void None %5
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%ptr_3 = OpFunctionParameter %_ptr_CrossWorkgroup_half
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%entry_3 = OpLabel
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%54 = OpExtInst %void %1 vstore_halfn_r %11 %uint_0 %ptr_3 RTN
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%55 = OpExtInst %void %1 vstore_halfn_r %16 %uint_0 %ptr_3 RTN
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%56 = OpExtInst %void %1 vstore_halfn_r %19 %uint_0 %ptr_3 RTN
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%57 = OpExtInst %void %1 vstore_halfn_r %22 %uint_0 %ptr_3 RTN
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%58 = OpExtInst %void %1 vstore_halfn_r %25 %uint_0 %ptr_3 RTN
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OpReturn
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OpFunctionEnd
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