derek.holloway
7502bf64a4
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350 lines
8.4 KiB
D
350 lines
8.4 KiB
D
#as: -m32rx --no-warn-explicit-parallel-conflicts --hidden -O
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#objdump: -dr
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#name: m32rx
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.*: +file format .*
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Disassembly of section .text:
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0+0000 <bcl>:
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0: 78 00 f0 00 bcl 0 <bcl> \|\| nop
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0+0004 <bncl>:
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4: 79 ff f0 00 bncl 0 <bcl> \|\| nop
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0+0008 <cmpz>:
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8: 00 7d f0 00 cmpz fp \|\| nop
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0+000c <cmpeq>:
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c: 0d 6d f0 00 cmpeq fp,fp \|\| nop
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0+0010 <maclh1>:
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10: 5d cd f0 00 maclh1 fp,fp \|\| nop
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0+0014 <msblo>:
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14: 5d dd f0 00 msblo fp,fp \|\| nop
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0+0018 <mulwu1>:
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18: 5d ad f0 00 mulwu1 fp,fp \|\| nop
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0+001c <macwu1>:
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1c: 5d bd f0 00 macwu1 fp,fp \|\| nop
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0+0020 <sadd>:
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20: 50 e4 f0 00 sadd \|\| nop
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0+0024 <satb>:
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24: 8d 6d 03 00 satb fp,fp
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0+0028 <mulhi>:
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28: 3d 8d f0 00 mulhi fp,fp,a1 \|\| nop
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0+002c <mullo>:
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2c: 3d 1d f0 00 mullo fp,fp \|\| nop
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0+0030 <divh>:
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30: 9d 0d 00 10 divh fp,fp
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0+0034 <machi>:
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34: 3d cd f0 00 machi fp,fp,a1 \|\| nop
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0+0038 <maclo>:
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38: 3d 5d f0 00 maclo fp,fp \|\| nop
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0+003c <mvfachi>:
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3c: 5d f4 f0 00 mvfachi fp,a1 \|\| nop
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0+0040 <mvfacmi>:
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40: 5d f6 f0 00 mvfacmi fp,a1 \|\| nop
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0+0044 <mvfaclo>:
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44: 5d f5 f0 00 mvfaclo fp,a1 \|\| nop
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0+0048 <mvtachi>:
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48: 5d 74 f0 00 mvtachi fp,a1 \|\| nop
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0+004c <mvtaclo>:
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4c: 5d 71 f0 00 mvtaclo fp \|\| nop
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0+0050 <rac>:
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50: 54 90 f0 00 rac a1 \|\| nop
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0+0054 <rac_ds>:
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54: 54 90 f0 00 rac a1 \|\| nop
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0+0058 <rac_dsi>:
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58: 50 94 f0 00 rac a0,a1 \|\| nop
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0+005c <rach>:
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5c: 54 80 f0 00 rach a1 \|\| nop
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0+0060 <rach_ds>:
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60: 50 84 f0 00 rach a0,a1 \|\| nop
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0+0064 <rach_dsi>:
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64: 54 81 f0 00 rach a1,a0,#0x2 \|\| nop
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0+0068 <bc__add>:
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68: 7c 00 8d ad bc 68 <bc__add> \|\| add fp,fp
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68: R_M32R_10_PCREL_RELA bcl
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6c: 7c 00 0d ad bc 6c <bc__add\+0x4> -> add fp,fp
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6c: R_M32R_10_PCREL_RELA bcl
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0+0070 <bcl__addi>:
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70: 78 00 cd 4d bcl 70 <bcl__addi> \|\| addi fp,#77
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70: R_M32R_10_PCREL_RELA bcl
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74: 78 00 cd 4d bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
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74: R_M32R_10_PCREL_RELA bcl
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0+0078 <bl__addv>:
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78: 7e 00 8d 8d bl 78 <bl__addv> \|\| addv fp,fp
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78: R_M32R_10_PCREL_RELA bcl
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7c: 7e 00 8d 8d bl 7c <bl__addv\+0x4> \|\| addv fp,fp
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7c: R_M32R_10_PCREL_RELA bcl
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0+0080 <bnc__addx>:
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80: 7d 00 8d 9d bnc 80 <bnc__addx> \|\| addx fp,fp
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80: R_M32R_10_PCREL_RELA bcl
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84: 7d 00 0d 9d bnc 84 <bnc__addx\+0x4> -> addx fp,fp
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84: R_M32R_10_PCREL_RELA bcl
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0+0088 <bncl__and>:
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88: 79 00 8d cd bncl 88 <bncl__and> \|\| and fp,fp
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88: R_M32R_10_PCREL_RELA bcl
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8c: 79 00 8d cd bncl 8c <bncl__and\+0x4> \|\| and fp,fp
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8c: R_M32R_10_PCREL_RELA bcl
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0+0090 <bra__cmp>:
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90: 7f 00 8d 4d bra 90 <bra__cmp> \|\| cmp fp,fp
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90: R_M32R_10_PCREL_RELA bcl
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94: 7f 00 8d 4d bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
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94: R_M32R_10_PCREL_RELA bcl
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0+0098 <jl__cmpeq>:
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98: 1e cd 8d 6d jl fp \|\| cmpeq fp,fp
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9c: 1e cd 8d 6d jl fp \|\| cmpeq fp,fp
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0+00a0 <jmp__cmpu>:
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a0: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
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a4: 1f cd 8d 5d jmp fp \|\| cmpu fp,fp
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0+00a8 <ld__cmpz>:
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a8: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
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ac: 2d cd 80 71 ld fp,@fp \|\| cmpz r1
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0+00b0 <ld__ldi>:
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b0: 2d e1 e2 4d ld fp,@r1\+ \|\| ldi r2,#77
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b4: 2d e1 e2 4d ld fp,@r1\+ \|\| ldi r2,#77
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0+00b8 <ldb__mv>:
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b8: 2d 8d 92 8d ldb fp,@fp \|\| mv r2,fp
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bc: 2d 8d 12 8d ldb fp,@fp -> mv r2,fp
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0+00c0 <ldh__neg>:
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c0: 2d ad 82 3d ldh fp,@fp \|\| neg r2,fp
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c4: 2d ad 02 3d ldh fp,@fp -> neg r2,fp
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0+00c8 <ldub__nop>:
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c8: 2d 9d f0 00 ldub fp,@fp \|\| nop
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cc: 2d 9d f0 00 ldub fp,@fp \|\| nop
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0+00d0 <lduh__not>:
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d0: 2d bd 82 bd lduh fp,@fp \|\| not r2,fp
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d4: 2d bd 02 bd lduh fp,@fp -> not r2,fp
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0+00d8 <lock__or>:
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d8: 2d dd 82 ed lock fp,@fp \|\| or r2,fp
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dc: 2d dd 02 ed lock fp,@fp -> or r2,fp
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0+00e0 <mvfc__sub>:
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e0: 1d 91 82 2d mvfc fp,cbr \|\| sub r2,fp
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e4: 1d 91 02 2d mvfc fp,cbr -> sub r2,fp
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0+00e8 <mvtc__subv>:
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e8: 12 ad 82 0d mvtc fp,spi \|\| subv r2,fp
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ec: 12 ad 82 0d mvtc fp,spi \|\| subv r2,fp
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0+00f0 <rte__subx>:
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f0: 10 d6 82 2d rte \|\| sub r2,fp
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f4: 10 d6 02 1d rte -> subx r2,fp
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0+00f8 <sll__xor>:
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f8: 1d 41 82 dd sll fp,r1 \|\| xor r2,fp
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fc: 1d 41 02 dd sll fp,r1 -> xor r2,fp
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0+0100 <slli__machi>:
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100: 5d 56 b2 4d slli fp,#0x16 \|\| machi r2,fp
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104: 5d 56 32 4d slli fp,#0x16 -> machi r2,fp
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0+0108 <sra__maclh1>:
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108: 1d 2d d2 cd sra fp,fp \|\| maclh1 r2,fp
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10c: 1d 2d 52 cd sra fp,fp -> maclh1 r2,fp
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0+0110 <srai__maclo>:
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110: 5d 36 b2 5d srai fp,#0x16 \|\| maclo r2,fp
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114: 5d 36 32 5d srai fp,#0x16 -> maclo r2,fp
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0+0118 <srl__macwhi>:
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118: 1d 0d b2 6d srl fp,fp \|\| macwhi r2,fp
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11c: 1d 0d 32 6d srl fp,fp -> macwhi r2,fp
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0+0120 <srli__macwlo>:
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120: 5d 16 b2 7d srli fp,#0x16 \|\| macwlo r2,fp
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124: 5d 16 32 7d srli fp,#0x16 -> macwlo r2,fp
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0+0128 <st__macwu1>:
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128: 2d 4d d2 bd st fp,@fp \|\| macwu1 r2,fp
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12c: 2d 4d d2 bd st fp,@fp \|\| macwu1 r2,fp
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0+0130 <st__msblo>:
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130: 2d 6d d2 dd st fp,@\+fp \|\| msblo r2,fp
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134: 2d 6d 52 dd st fp,@\+fp -> msblo r2,fp
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0+0138 <st__mul>:
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138: 2d 7d 92 6d st fp,@-fp \|\| mul r2,fp
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13c: 2d 7d 12 6d st fp,@-fp -> mul r2,fp
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0+0140 <stb__mulhi>:
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140: 2d 0d b2 0d stb fp,@fp \|\| mulhi r2,fp
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144: 2d 0d b2 0d stb fp,@fp \|\| mulhi r2,fp
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0+0148 <sth__mullo>:
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148: 2d 2d b2 1d sth fp,@fp \|\| mullo r2,fp
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14c: 2d 2d b2 1d sth fp,@fp \|\| mullo r2,fp
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0+0150 <trap__mulwhi>:
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150: 10 f2 b2 2d trap #0x2 \|\| mulwhi r2,fp
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154: 10 f2 f0 00 trap #0x2 \|\| nop
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158: 32 2d f0 00 mulwhi r2,fp \|\| nop
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0+015c <unlock__mulwlo>:
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15c: 2d 5d b2 3d unlock fp,@fp \|\| mulwlo r2,fp
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160: 2d 5d b2 3d unlock fp,@fp \|\| mulwlo r2,fp
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0+0164 <add__mulwu1>:
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164: 0d ad d2 ad add fp,fp \|\| mulwu1 r2,fp
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168: 0d ad 52 ad add fp,fp -> mulwu1 r2,fp
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0+016c <addi__mvfachi>:
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16c: 4d 4d d2 f0 addi fp,#77 \|\| mvfachi r2
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170: 4d 4d d2 f0 addi fp,#77 \|\| mvfachi r2
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0+0174 <addv__mvfaclo>:
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174: 0d 8d d2 f5 addv fp,fp \|\| mvfaclo r2,a1
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178: 0d 8d d2 f5 addv fp,fp \|\| mvfaclo r2,a1
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0+017c <addx__mvfacmi>:
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17c: 0d 9d d2 f2 addx fp,fp \|\| mvfacmi r2
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180: 0d 9d d2 f2 addx fp,fp \|\| mvfacmi r2
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0+0184 <and__mvtachi>:
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184: 0d cd d2 70 and fp,fp \|\| mvtachi r2
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188: 0d cd d2 70 and fp,fp \|\| mvtachi r2
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0+018c <cmp__mvtaclo>:
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18c: 0d 4d d2 71 cmp fp,fp \|\| mvtaclo r2
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190: 0d 4d d2 71 cmp fp,fp \|\| mvtaclo r2
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0+0194 <cmpeq__rac>:
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194: 0d 6d d4 90 cmpeq fp,fp \|\| rac a1
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198: 0d 6d d4 90 cmpeq fp,fp \|\| rac a1
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0+019c <cmpu__rach>:
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19c: 0d 5d d0 84 cmpu fp,fp \|\| rach a0,a1
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1a0: 0d 5d d4 84 cmpu fp,fp \|\| rach a1,a1
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0+01a4 <cmpz__sadd>:
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1a4: 00 7d d0 e4 cmpz fp \|\| sadd
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1a8: 00 7d d0 e4 cmpz fp \|\| sadd
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0+01ac <sc>:
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1ac: 74 01 d0 e4 sc \|\| sadd
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0+01b0 <snc>:
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1b0: 75 01 d0 e4 snc \|\| sadd
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0+01b4 <jc>:
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1b4: 1c cd f0 00 jc fp \|\| nop
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0+01b8 <jnc>:
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1b8: 1d cd f0 00 jnc fp \|\| nop
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0+01bc <pcmpbz>:
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1bc: 03 7d f0 00 pcmpbz fp \|\| nop
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0+01c0 <sat>:
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1c0: 8d 6d 00 00 sat fp,fp
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0+01c4 <sath>:
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1c4: 8d 6d 02 00 sath fp,fp
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0+01c8 <jc__pcmpbz>:
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1c8: 1c cd 83 7d jc fp \|\| pcmpbz fp
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1cc: 1c cd 03 7d jc fp -> pcmpbz fp
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0+01d0 <jnc__ldi>:
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1d0: 1d cd ed 4d jnc fp \|\| ldi fp,#77
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1d4: 1d cd 6d 4d jnc fp -> ldi fp,#77
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0+01d8 <sc__mv>:
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1d8: 74 01 9d 82 sc \|\| mv fp,r2
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1dc: 74 01 9d 82 sc \|\| mv fp,r2
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0+01e0 <snc__neg>:
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1e0: 75 01 8d 32 snc \|\| neg fp,r2
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1e4: 75 01 8d 32 snc \|\| neg fp,r2
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0+01e8 <nop__sadd>:
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1e8: 70 00 d0 e4 nop \|\| sadd
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0+01ec <sadd__nop>:
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1ec: 70 00 d0 e4 nop \|\| sadd
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0+01f0 <sadd__nop_reverse>:
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1f0: 70 00 d0 e4 nop \|\| sadd
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0+01f4 <add__not>:
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1f4: 00 a1 83 b5 add r0,r1 \|\| not r3,r5
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0+01f8 <add__not_dest_clash>:
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1f8: 03 a4 03 b5 add r3,r4 -> not r3,r5
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0+01fc <add__not__src_clash>:
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1fc: 03 a4 05 b3 add r3,r4 -> not r5,r3
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0+0200 <add__not__no_clash>:
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200: 03 a4 84 b5 add r3,r4 \|\| not r4,r5
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0+0204 <mul__sra>:
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204: 13 24 91 62 sra r3,r4 \|\| mul r1,r2
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0+0208 <mul__sra__reverse_src_clash>:
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208: 13 24 91 63 sra r3,r4 \|\| mul r1,r3
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0+020c <bc__add_>:
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20c: 7c 04 01 a2 bc 21c <label> -> add r1,r2
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0+0210 <add__bc>:
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210: 7c 03 83 a4 bc 21c <label> \|\| add r3,r4
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0+0214 <bc__add__forced_parallel>:
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214: 7c 02 85 a6 bc 21c <label> \|\| add r5,r6
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0+0218 <add__bc__forced_parallel>:
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218: 7c 01 87 a8 bc 21c <label> \|\| add r7,r8
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0+021c <label>:
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21c: 70 00 f0 00 nop \|\| nop
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0+0220 <mulwhi>:
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220: 3d 2d 3d ad mulwhi fp,fp -> mulwhi fp,fp,a1
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0+0224 <mulwlo>:
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224: 3d 3d 3d bd mulwlo fp,fp -> mulwlo fp,fp,a1
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0+0228 <macwhi>:
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228: 3d 6d 3d ed macwhi fp,fp -> macwhi fp,fp,a1
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0+022c <macwlo>:
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22c: 3d 7d 3d fd macwlo fp,fp -> macwlo fp,fp,a1
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