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102 lines
3.9 KiB
C++
102 lines
3.9 KiB
C++
/*******************************************************************************
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*
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* MIT License
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*
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* Copyright 2024-2025 AMD ROCm(TM) Software
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#include <rocRoller/Scheduling/Observers/VGPRIndexingObserver.hpp>
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#include <rocRoller/Scheduling/Observers/VGPRIndexingObserver_detail.hpp>
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#include <rocRoller/KernelOptions_detail.hpp>
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namespace rocRoller
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{
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namespace Scheduling
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{
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void VGPRIndexingObserver::modify(Instruction& inst) const
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{
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using namespace VGPRIndexingObserverDetail;
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auto context = m_context.lock();
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auto const& architecture = context->targetArchitecture();
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GPUInstructionInfo info = architecture.GetInstructionInfo(inst.getOpCode());
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if(info.isBranch() or inst.isLabel())
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{
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// Conservatively reset MODE register before branches and labels.
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inst.setModeRegister(0);
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return;
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}
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uint8_t modeSet = 0b0;
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bool foundVgprOperand = false;
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auto checkOperandsForMode = [&](auto const& operands,
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uint maxOperands,
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uint shift,
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uint iterShift) {
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for(auto const& operand : operands)
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{
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if(operand and operand->regType() == Register::Type::Vector)
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{
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foundVgprOperand = true;
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int idx = *operand->registerIndices().begin();
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modeSet |= (GetBankBits(idx) << shift);
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Log::debug(
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"[ VGPR indexing observer ]: operand for {}: {}, index: {} bank: {} ",
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inst.getOpCode(),
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operand->toString(),
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idx,
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GetBankBits(idx));
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if(--maxOperands == 0)
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break;
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}
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shift += iterShift;
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}
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};
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// Process 1 dst
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checkOperandsForMode(inst.getDsts(), 1, 6, 0);
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// Process 3 srcs
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checkOperandsForMode(inst.getSrcs(), 3, 0, 2);
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if(foundVgprOperand and m_modeSet != modeSet)
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{
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Log::debug("[ VGPR indexing observer ]: MODE reg for {}: 0x{:02X}",
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inst.getOpCode(),
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modeSet);
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inst.setModeRegister(modeSet);
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}
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}
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void VGPRIndexingObserver::observe(Instruction const& inst)
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{
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if(inst.getModeRegister())
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m_modeSet = *inst.getModeRegister();
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}
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}
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}
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