derek.holloway
7502bf64a4
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77 lines
3.0 KiB
ArmAsm
77 lines
3.0 KiB
ArmAsm
// Verify that splitting a two-address DS exchange normalizes all three of its
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// VGPR roles against their own incoming banks. Unlike a DS load, the exchange
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// carries {Dst, Src0, Src1}, and mode 0x41 gives them a mix of banks: the
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// destination tuple and the address are bank 1 while the data operands are
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// bank 0. Rebasing every role from a single assumed bank would silently
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// redirect the address or the data.
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --output %t.out.elf 2>&1 | %FileCheck --check-prefix=API %s
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// API-NOT: error:
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// API: RESULT: SUCCESS
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=DISASM %s
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// DISASM-LABEL: <test_ds_storexchg_vgpr_msb>:
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// DISASM: s_set_vgpr_msb 0x41
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// DISASM-NEXT: s_branch
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// COM: The compound exchange must not survive in .text.
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// DISASM-NOT: ds_storexchg_2addr
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// COM: The first half stays under the incoming mode: destination v[254:255]
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// COM: and address v88 keep their bank-1 identity, and the bank-0 data pair is
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// COM: not rebased. Rebasing any role from bank zero would instead emit a mode
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// COM: transition here, so no s_set_vgpr_msb may precede the first half.
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// DISASM-NOT: s_set_vgpr_msb
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// DISASM: ds_storexchg_rtn_b64 v[254:255], v88, v[100:101] offset:680
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// COM: Only the destination moves to the next bank for the second half; src0
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// COM: stays at bank 1 (v88 -> v344) and src1 stays at bank 0.
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// DISASM-NEXT: s_set_vgpr_msb 0x4181
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// DISASM-NEXT: ds_storexchg_rtn_b64 v[0:1]{{.*v\[512:513\].*}}v88{{.*v344.*}}v[102:103] offset:688
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// DISASM-NEXT: s_set_vgpr_msb 0x8141
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// DISASM-NEXT: s_wait_dscnt 0x0
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// DISASM: s_branch
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// RUN: hotswap-rewrite %t.out.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --check-idempotent | %FileCheck --check-prefix=IDEM %s
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// IDEM: IDEMPOTENT: YES
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_ds_storexchg_vgpr_msb
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.p2align 8
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.type test_ds_storexchg_vgpr_msb,@function
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test_ds_storexchg_vgpr_msb:
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s_set_vgpr_msb 0x41
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ds_storexchg_2addr_rtn_b64 v[254:257], v88, v[100:101], v[102:103] offset0:85 offset1:86
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s_wait_dscnt 0x0
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s_endpgm
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.Ltest_ds_storexchg_vgpr_msb_end:
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.size test_ds_storexchg_vgpr_msb, .Ltest_ds_storexchg_vgpr_msb_end-test_ds_storexchg_vgpr_msb
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.rodata
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.p2align 8
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.amdhsa_kernel test_ds_storexchg_vgpr_msb
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.amdhsa_next_free_vgpr 688
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.amdhsa_next_free_sgpr 2
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.amdhsa_wavefront_size32 1
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.end_amdhsa_kernel
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.amdgpu_metadata
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amdhsa.version:
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- 3
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- 0
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amdhsa.kernels:
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- .name: test_ds_storexchg_vgpr_msb
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.symbol: test_ds_storexchg_vgpr_msb.kd
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.sgpr_count: 2
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.vgpr_count: 688
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.kernarg_segment_size: 0
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.group_segment_fixed_size: 0
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.private_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.wavefront_size: 32
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.max_flat_workgroup_size: 256
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.end_amdgpu_metadata
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