derek.holloway
7502bf64a4
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402 lines
13 KiB
ArmAsm
402 lines
13 KiB
ArmAsm
// COM: Test v_cvt_pk_fp8_f32 CLAMP=1 (E5M3) full conversion patch.
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// COM:
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// COM: Creates a minimal gfx1250 code object containing v_cvt_pk_fp8_f32
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// COM: with clamp (E5M3 mode), runs the hotswap rewrite, and verifies the
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// COM: replacement sequence covers: NaN detection, base F32->F16->UE5M3
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// COM: conversion, RTE rounding, overflow clamping, NaN override, literal
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// COM: sources, mixed literal/register sources, non-inline fractional
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// COM: literals, and inline F32 constants.
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// COM:
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// COM: Companion tests:
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// COM: hotswap-cvt-fp8-modifiers.s - source modifier variants
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// COM: hotswap-cvt-fp8-nosled.s - trampoline fallback path
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// COM: hotswap-cvt-fp8-multi.s - multi-site stacking
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// RUN: %clang -target amdgcn-amd-amdhsa -mcpu=gfx1250 -nostdlib %s -o %t.elf
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// RUN: env AMD_COMGR_EMIT_VERBOSE_LOGS=1 hotswap-rewrite %t.elf \
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// RUN: amdgcn-amd-amdhsa--gfx1250 amdgcn-amd-amdhsa--gfx1250 \
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// RUN: --dump %t.out.elf --check-idempotent 2>&1 \
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// RUN: | %FileCheck --check-prefix=API %s
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// API: hotswap: liveness: kernel test_cvt_pk_fp8_literal:
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// API-SAME: sgprs_before=2, sgprs_after=6
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// API: REWRITE: SUCCESS
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// API: IDEMPOTENT: YES
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=LOW %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=HIGH %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=NOCLAMP %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=LITERAL %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=MIXED0 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=MIXED1 %s
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// RUN: %llvm-objdump -d %t.out.elf | %FileCheck --check-prefix=INLINE %s
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// ---- Kernel 1: CLAMP=1, low half (should be patched) --------------------------
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//
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// COM: Original site is replaced with s_branch. Trampoline body: VCC save,
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// COM: two per-source F32->UE5M3 conversions (23 instructions each), pack
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// COM: into 16-bit pair, merge into low half of vdst via v_bfi_b32, VCC restore.
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// LOW-LABEL: <test_cvt_pk_fp8_low>:
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// LOW: s_branch
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// COM: --- VCC save ---
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// LOW: s_mov_b32
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// COM: --- src0 conversion ---
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// LOW-NEXT: v_and_b32{{.*}}0x7fffffff, v1
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// LOW-NEXT: v_cmp_lt_u32{{.*}}0x7f800000
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_max_num_f32{{.*}}, 0, v1
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// LOW-NEXT: v_cmp_le_f32{{.*}}0x47780000
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_mul_f32{{.*}}0x39000000
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// LOW-NEXT: v_cvt_nearest_i32_f32
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// LOW-NEXT: v_add{{.*}}0xf0
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// LOW-NEXT: v_min_u32{{.*}}0xfe
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// LOW-NEXT: v_cvt_f16_f32
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// LOW-NEXT: v_and_b32
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// LOW-NEXT: v_bfe_u32
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// LOW-NEXT: v_lshlrev_b32
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// LOW-NEXT: v_bfi_b32
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// LOW-NEXT: v_cmp_lt_u32{{.*}}0x80
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// LOW-NEXT: v_add_co_ci_u32
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// LOW-NEXT: v_min_u32{{.*}}0xfe
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_cndmask_b32
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_mov_b32
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// LOW-NEXT: v_cndmask_b32
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// COM: --- src1 conversion ---
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// LOW-NEXT: v_and_b32{{.*}}0x7fffffff, v2
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// LOW-NEXT: v_cmp_lt_u32{{.*}}0x7f800000
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_max_num_f32{{.*}}, 0, v2
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// LOW-NEXT: v_cmp_le_f32{{.*}}0x47780000
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_mul_f32{{.*}}0x39000000
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// LOW-NEXT: v_cvt_nearest_i32_f32
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// LOW-NEXT: v_add{{.*}}0xf0
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// LOW-NEXT: v_min_u32{{.*}}0xfe
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// LOW-NEXT: v_cvt_f16_f32
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// LOW-NEXT: v_and_b32
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// LOW-NEXT: v_bfe_u32
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// LOW-NEXT: v_lshlrev_b32
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// LOW-NEXT: v_bfi_b32
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// LOW-NEXT: v_cmp_lt_u32{{.*}}0x80
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// LOW-NEXT: v_add_co_ci_u32
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// LOW-NEXT: v_min_u32{{.*}}0xfe
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_cndmask_b32
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// LOW-NEXT: s_mov_b32
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// LOW-NEXT: v_mov_b32
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// LOW-NEXT: v_cndmask_b32
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// COM: --- pack + merge (low half) ---
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// LOW-NEXT: v_lshl_or_b32
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// LOW-NEXT: v_bfi_b32 v0,
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// COM: --- VCC restore ---
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// LOW-NEXT: s_mov_b32
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.amdgcn_target "amdgcn-amd-amdhsa--gfx1250"
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.text
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.globl test_cvt_pk_fp8_low
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.p2align 8
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.type test_cvt_pk_fp8_low,@function
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test_cvt_pk_fp8_low:
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v_cvt_pk_fp8_f32 v0, v1, v2 clamp
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s_endpgm
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.Ltest_cvt_pk_fp8_low_end:
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.size test_cvt_pk_fp8_low, .Ltest_cvt_pk_fp8_low_end-test_cvt_pk_fp8_low
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// ---- Kernel 2: CLAMP=1, high half (raw encoding for op_sel[3]=1) --------------
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//
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// COM: Same conversion sequence as low, but final merge uses shift + bfi to
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// COM: write the packed bytes into the upper 16 bits of vdst.
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// HIGH-LABEL: <test_cvt_pk_fp8_high>:
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// HIGH: s_branch
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// COM: --- VCC save + src0 conversion (anchor on unique src v6) ---
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// HIGH: v_and_b32{{.*}}0x7fffffff, v6
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// HIGH-NEXT: v_cmp_lt_u32{{.*}}0x7f800000
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_max_num_f32{{.*}}, 0, v6
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// HIGH-NEXT: v_cmp_le_f32{{.*}}0x47780000
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_mul_f32{{.*}}0x39000000
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// HIGH-NEXT: v_cvt_nearest_i32_f32
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// HIGH-NEXT: v_add{{.*}}0xf0
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// HIGH-NEXT: v_min_u32{{.*}}0xfe
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// HIGH-NEXT: v_cvt_f16_f32
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// HIGH-NEXT: v_and_b32
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// HIGH-NEXT: v_bfe_u32
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// HIGH-NEXT: v_lshlrev_b32
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// HIGH-NEXT: v_bfi_b32
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// HIGH-NEXT: v_cmp_lt_u32{{.*}}0x80
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// HIGH-NEXT: v_add_co_ci_u32
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// HIGH-NEXT: v_min_u32{{.*}}0xfe
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_cndmask_b32
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_mov_b32
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// HIGH-NEXT: v_cndmask_b32
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// COM: --- src1 conversion ---
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// HIGH-NEXT: v_and_b32{{.*}}0x7fffffff, v7
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// HIGH-NEXT: v_cmp_lt_u32{{.*}}0x7f800000
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_max_num_f32{{.*}}, 0, v7
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// HIGH-NEXT: v_cmp_le_f32{{.*}}0x47780000
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_mul_f32{{.*}}0x39000000
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// HIGH-NEXT: v_cvt_nearest_i32_f32
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// HIGH-NEXT: v_add{{.*}}0xf0
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// HIGH-NEXT: v_min_u32{{.*}}0xfe
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// HIGH-NEXT: v_cvt_f16_f32
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// HIGH-NEXT: v_and_b32
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// HIGH-NEXT: v_bfe_u32
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// HIGH-NEXT: v_lshlrev_b32
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// HIGH-NEXT: v_bfi_b32
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// HIGH-NEXT: v_cmp_lt_u32{{.*}}0x80
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// HIGH-NEXT: v_add_co_ci_u32
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// HIGH-NEXT: v_min_u32{{.*}}0xfe
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_cndmask_b32
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// HIGH-NEXT: s_mov_b32
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// HIGH-NEXT: v_mov_b32
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// HIGH-NEXT: v_cndmask_b32
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// COM: --- pack + merge (high half: shift + bfi) ---
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// HIGH-NEXT: v_lshl_or_b32
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// HIGH-NEXT: v_lshlrev_b32
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// HIGH-NEXT: v_bfi_b32 v5,
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// COM: --- VCC restore ---
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// HIGH-NEXT: s_mov_b32
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.globl test_cvt_pk_fp8_high
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.p2align 8
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.type test_cvt_pk_fp8_high,@function
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test_cvt_pk_fp8_high:
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// v_cvt_pk_fp8_f32 v5, v6, v7 clamp op_sel:[0,0,0,1]
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// dword0 = 0xD769C005 (bit14=1 op_sel[3], bit15=1 CLAMP, vdst=v5)
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// dword1 = 0x02020F06 (src0=v6, src1=v7, no modifiers)
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.long 0xD769C005
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.long 0x02020F06
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s_endpgm
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.Ltest_cvt_pk_fp8_high_end:
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.size test_cvt_pk_fp8_high, .Ltest_cvt_pk_fp8_high_end-test_cvt_pk_fp8_high
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// ---- Kernel 3: no clamp (should NOT be patched) -------------------------------
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// NOCLAMP-LABEL: <test_cvt_pk_fp8_noclamp>:
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// NOCLAMP-NEXT: v_cvt_pk_fp8_f32
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.globl test_cvt_pk_fp8_noclamp
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.p2align 8
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.type test_cvt_pk_fp8_noclamp,@function
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test_cvt_pk_fp8_noclamp:
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v_cvt_pk_fp8_f32 v10, v11, v12
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s_endpgm
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.Ltest_cvt_pk_fp8_noclamp_end:
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.size test_cvt_pk_fp8_noclamp, .Ltest_cvt_pk_fp8_noclamp_end-test_cvt_pk_fp8_noclamp
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// ---- Kernel 4: CLAMP=1 with literal F32 sources (12-byte encoding) -----------
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//
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// COM: Literal VOP3 operands are decoded as immediate MC operands and extend
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// COM: the instruction to 12 bytes. The patch materializes the literal into
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// COM: scratch VGPRs before running the normal per-source conversion sequence.
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// COM: The replacement body can be emitted into any nearby NOP sled, so this
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// COM: check verifies the original 12-byte slot and the generated body rather
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// COM: than a specific sled label.
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// LITERAL-LABEL: <test_cvt_pk_fp8_literal>:
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// LITERAL-NEXT: s_branch
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// LITERAL-NEXT: s_nop
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// LITERAL-NEXT: s_nop
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// LITERAL-NEXT: s_endpgm
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// LITERAL: v_mov_b32{{.*}}0x477f0000
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// LITERAL-NEXT: v_mov_b32{{.*}}0x477f0000
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// LITERAL-NEXT: v_and_b32{{.*}}0x7fffffff
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// LITERAL: v_cmp_le_f32{{.*}}0x47780000
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// LITERAL: v_lshl_or_b32
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// LITERAL-NEXT: v_bfi_b32 v4,
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// LITERAL: s_branch{{.*}}<test_cvt_pk_fp8_literal+0xc>
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.globl test_cvt_pk_fp8_literal
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.p2align 8
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.type test_cvt_pk_fp8_literal,@function
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test_cvt_pk_fp8_literal:
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v_cvt_pk_fp8_f32 v4, 0x477f0000, 0x477f0000 clamp
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s_endpgm
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.Ltest_cvt_pk_fp8_literal_end:
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.size test_cvt_pk_fp8_literal, .Ltest_cvt_pk_fp8_literal_end-test_cvt_pk_fp8_literal
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// ---- Kernel 5: 12-byte literal src0, register src1 --------------------------
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// MIXED0-LABEL: <test_cvt_pk_fp8_literal_src0>:
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// MIXED0-NEXT: s_branch
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// MIXED0-NEXT: s_nop
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// MIXED0-NEXT: s_nop
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// MIXED0-NEXT: s_endpgm
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// MIXED0: v_mov_b32{{.*}}0x477f0000
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// MIXED0: v_and_b32{{.*}}0x7fffffff
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// MIXED0: v_and_b32{{.*}}0x7fffffff, v17
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// MIXED0: v_bfi_b32 v16,
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// MIXED0: s_branch{{.*}}<test_cvt_pk_fp8_literal_src0+0xc>
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.globl test_cvt_pk_fp8_literal_src0
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.p2align 8
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.type test_cvt_pk_fp8_literal_src0,@function
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test_cvt_pk_fp8_literal_src0:
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v_cvt_pk_fp8_f32 v16, 0x477f0000, v17 clamp
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s_endpgm
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.Ltest_cvt_pk_fp8_literal_src0_end:
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.size test_cvt_pk_fp8_literal_src0, .Ltest_cvt_pk_fp8_literal_src0_end-test_cvt_pk_fp8_literal_src0
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// ---- Kernel 6: register src0, 12-byte literal src1 --------------------------
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// MIXED1-LABEL: <test_cvt_pk_fp8_literal_src1>:
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// MIXED1-NEXT: s_branch
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// MIXED1-NEXT: s_nop
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// MIXED1-NEXT: s_nop
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// MIXED1-NEXT: s_endpgm
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// MIXED1: v_mov_b32{{.*}}0x3eaaaaab
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// MIXED1: v_and_b32{{.*}}0x7fffffff, v21
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// MIXED1: v_and_b32{{.*}}0x7fffffff
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// MIXED1: v_bfi_b32 v20,
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// MIXED1: s_branch{{.*}}<test_cvt_pk_fp8_literal_src1+0xc>
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.globl test_cvt_pk_fp8_literal_src1
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.p2align 8
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.type test_cvt_pk_fp8_literal_src1,@function
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test_cvt_pk_fp8_literal_src1:
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v_cvt_pk_fp8_f32 v20, v21, 0.3333333432674408 clamp
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s_endpgm
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.Ltest_cvt_pk_fp8_literal_src1_end:
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.size test_cvt_pk_fp8_literal_src1, .Ltest_cvt_pk_fp8_literal_src1_end-test_cvt_pk_fp8_literal_src1
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// ---- Kernel 7: inline fractional constants (8-byte encoding) ----------------
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// INLINE-LABEL: <test_cvt_pk_fp8_inline_constants>:
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// INLINE-NEXT: s_branch
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// INLINE-NEXT: s_nop
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// INLINE-NEXT: s_endpgm
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// INLINE: v_mov_b32{{.*}}1.0
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// INLINE-NEXT: v_mov_b32{{.*}}0.5
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// INLINE-NEXT: v_and_b32{{.*}}0x7fffffff
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// INLINE: v_lshl_or_b32
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// INLINE-NEXT: v_bfi_b32 v24,
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// INLINE: s_branch{{.*}}<test_cvt_pk_fp8_inline_constants+0x8>
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.globl test_cvt_pk_fp8_inline_constants
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.p2align 8
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.type test_cvt_pk_fp8_inline_constants,@function
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test_cvt_pk_fp8_inline_constants:
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v_cvt_pk_fp8_f32 v24, 1.0, 0.5 clamp
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s_endpgm
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.Ltest_cvt_pk_fp8_inline_constants_end:
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.size test_cvt_pk_fp8_inline_constants, .Ltest_cvt_pk_fp8_inline_constants_end-test_cvt_pk_fp8_inline_constants
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.rodata
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.p2align 8
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.amdhsa_kernel test_cvt_pk_fp8_low
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.amdhsa_next_free_vgpr 3
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_pk_fp8_high
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.amdhsa_next_free_vgpr 8
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_pk_fp8_noclamp
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.amdhsa_next_free_vgpr 13
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_pk_fp8_literal
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.amdhsa_next_free_vgpr 5
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
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.amdhsa_kernel test_cvt_pk_fp8_literal_src0
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.amdhsa_next_free_vgpr 18
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.amdhsa_next_free_sgpr 2
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.end_amdhsa_kernel
|
|
.amdhsa_kernel test_cvt_pk_fp8_literal_src1
|
|
.amdhsa_next_free_vgpr 22
|
|
.amdhsa_next_free_sgpr 2
|
|
.end_amdhsa_kernel
|
|
.amdhsa_kernel test_cvt_pk_fp8_inline_constants
|
|
.amdhsa_next_free_vgpr 25
|
|
.amdhsa_next_free_sgpr 2
|
|
.end_amdhsa_kernel
|
|
|
|
.amdgpu_metadata
|
|
amdhsa.version:
|
|
- 3
|
|
- 0
|
|
amdhsa.kernels:
|
|
- .name: test_cvt_pk_fp8_low
|
|
.symbol: test_cvt_pk_fp8_low.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 3
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_high
|
|
.symbol: test_cvt_pk_fp8_high.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 8
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_noclamp
|
|
.symbol: test_cvt_pk_fp8_noclamp.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 13
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_literal
|
|
.symbol: test_cvt_pk_fp8_literal.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 5
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_literal_src0
|
|
.symbol: test_cvt_pk_fp8_literal_src0.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 18
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_literal_src1
|
|
.symbol: test_cvt_pk_fp8_literal_src1.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 22
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
- .name: test_cvt_pk_fp8_inline_constants
|
|
.symbol: test_cvt_pk_fp8_inline_constants.kd
|
|
.sgpr_count: 2
|
|
.vgpr_count: 25
|
|
.kernarg_segment_size: 0
|
|
.group_segment_fixed_size: 0
|
|
.private_segment_fixed_size: 0
|
|
.kernarg_segment_align: 8
|
|
.wavefront_size: 64
|
|
.max_flat_workgroup_size: 256
|
|
.end_amdgpu_metadata
|