TheRock/compiler/amd-llvm/clang/test/CodeGen/RISCV/rvk-intrinsics/riscv32-zknh.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +zknh -emit-llvm %s -o - \
// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN:     | FileCheck %s  -check-prefix=RV32ZKNH

#include <riscv_crypto.h>

// RV32ZKNH-LABEL: @sha256sig0(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig0(i32 [[RS1:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha256sig0(uint32_t rs1) {
  return __riscv_sha256sig0(rs1);
}

// RV32ZKNH-LABEL: @sha256sig1(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sig1(i32 [[RS1:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha256sig1(uint32_t rs1) {
  return __riscv_sha256sig1(rs1);
}

// RV32ZKNH-LABEL: @sha256sum0(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum0(i32 [[RS1:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha256sum0(uint32_t rs1) {
  return __riscv_sha256sum0(rs1);
}

// RV32ZKNH-LABEL: @sha256sum1(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha256sum1(i32 [[RS1:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha256sum1(uint32_t rs1) {
  return __riscv_sha256sum1(rs1);
}

// RV32ZKNH-LABEL: @sha512sig0h(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig0h(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sig0h(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sig0h(rs1, rs2);
}

// RV32ZKNH-LABEL: @sha512sig0l(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig0l(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sig0l(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sig0l(rs1, rs2);
}

// RV32ZKNH-LABEL: @sha512sig1h(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig1h(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sig1h(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sig1h(rs1, rs2);
}

// RV32ZKNH-LABEL: @sha512sig1l(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sig1l(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sig1l(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sig1l(rs1, rs2);
}

// RV32ZKNH-LABEL: @sha512sum0r(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sum0r(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sum0r(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sum0r(rs1, rs2);
}

// RV32ZKNH-LABEL: @sha512sum1r(
// RV32ZKNH-NEXT:  entry:
// RV32ZKNH-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.sha512sum1r(i32 [[RS1:%.*]], i32 [[RS2:%.*]])
// RV32ZKNH-NEXT:    ret i32 [[TMP0]]
//
uint32_t sha512sum1r(uint32_t rs1, uint32_t rs2) {
  return __riscv_sha512sum1r(rs1, rs2);
}