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82 lines
4.2 KiB
ReStructuredText
82 lines
4.2 KiB
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..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx11_delay:
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delay
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=====
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A delay between dependent SALU/VALU instructions.
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This operand may specify a delay for 2 instructions:
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the one after the current *s_delay_alu* instruction
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and for the second instruction indicated by *SKIP*.
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The bits of this operand have the following meaning:
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===== ========================================================== ============
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Bits Description Value Range
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===== ========================================================== ============
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3:0 ID0: indicates a delay for the first instruction. 0..11
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6:4 SKIP: indicates the position of the second instruction. 0..5
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10:7 ID1: indicates a delay for the second instruction. 0..11
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===== ========================================================== ============
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from 0 to 0xFFFF.
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* A combination of *instid0*, *instskip*, *instid1* values which are described below.
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======================== =========================== ===============
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Syntax Description Default Value
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======================== =========================== ===============
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instid0(<*ID name*>) A symbolic *ID0* value. instid0(NO_DEP)
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instskip(<*SKIP name*>) A symbolic *SKIP* value. instskip(SAME)
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instid1(<*ID name*>) A symbolic *ID1* value. instid1(NO_DEP)
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======================== =========================== ===============
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These values may be specified in any order.
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When more than one value is specified, the values must be separated from each other by a '|'.
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Valid *ID names* are defined below.
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=================== ===================================================================
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Name Description
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=================== ===================================================================
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NO_DEP No dependency on any prior instruction. This is the default value.
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VALU_DEP_1 Dependency on a previous VALU instruction, 1 opcode back.
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VALU_DEP_2 Dependency on a previous VALU instruction, 2 opcodes back.
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VALU_DEP_3 Dependency on a previous VALU instruction, 3 opcodes back.
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VALU_DEP_4 Dependency on a previous VALU instruction, 4 opcodes back.
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TRANS32_DEP_1 Dependency on a previous TRANS32 instruction, 1 opcode back.
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TRANS32_DEP_2 Dependency on a previous TRANS32 instruction, 2 opcodes back.
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TRANS32_DEP_3 Dependency on a previous TRANS32 instruction, 3 opcodes back.
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FMA_ACCUM_CYCLE_1 Single cycle penalty for FMA accumulation.
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SALU_CYCLE_1 1 cycle penalty for a prior SALU instruction.
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SALU_CYCLE_2 2 cycle penalty for a prior SALU instruction.
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SALU_CYCLE_3 3 cycle penalty for a prior SALU instruction.
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=================== ===================================================================
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Legal *SKIP names* are described in the following table.
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======== ============================================================================
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Name Description
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======== ============================================================================
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SAME Apply second dependency to the same instruction. This is the default value.
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NEXT Apply second dependency to the next instruction.
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SKIP_1 Skip 1 instruction then apply dependency.
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SKIP_2 Skip 2 instructions then apply dependency.
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SKIP_3 Skip 3 instructions then apply dependency.
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SKIP_4 Skip 4 instructions then apply dependency.
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======== ============================================================================
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Examples:
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.. parsed-literal::
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s_delay_alu instid0(VALU_DEP_1)
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s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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