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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-redundant-sextinreg.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: sextload
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: sextload
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x0:_(p0) = COPY $x0
; CHECK-NEXT: %sextload:_(s32) = G_SEXTLOAD %x0(p0) :: (load (s16))
; CHECK-NEXT: $w0 = COPY %sextload(s32)
%x0:_(p0) = COPY $x0
%sextload:_(s32) = G_SEXTLOAD %x0:_(p0) :: (load (s16))
%sext_inreg:_(s32) = G_SEXT_INREG %sextload:_(s32), 24
$w0 = COPY %sext_inreg(s32)
...
---
name: assert_sext
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; The G_ASSERT_SEXT says we already sign extended from 24 bits, so the
; G_SEXT_INREG is not necessary.
; CHECK-LABEL: name: assert_sext
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w0:_(s32) = COPY $w0
; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
; CHECK-NEXT: $w0 = COPY %assert_sext(s32)
%w0:_(s32) = COPY $w0
%assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
%sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 24
$w0 = COPY %sext_inreg(s32)
...
---
name: assert_sext_greater_width
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; The G_ASSERT_SEXT is from a wider width than the G_SEXT_INREG, so we
; can't eliminate it.
; CHECK-LABEL: name: assert_sext_greater_width
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w0:_(s32) = COPY $w0
; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
; CHECK-NEXT: %sext_inreg:_(s32) = G_SEXT_INREG %assert_sext, 12
; CHECK-NEXT: $w0 = COPY %sext_inreg(s32)
%w0:_(s32) = COPY $w0
%assert_sext:_(s32) = G_ASSERT_SEXT %w0, 24
%sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
$w0 = COPY %sext_inreg(s32)
...
---
name: assert_sext_smaller_width
legalized: true
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $w0
; The G_ASSERT_SEXT is from a smaller width, so the G_SEXT_INREG is not
; necessary.
; CHECK-LABEL: name: assert_sext_smaller_width
; CHECK: liveins: $w0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w0:_(s32) = COPY $w0
; CHECK-NEXT: %assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
; CHECK-NEXT: $w0 = COPY %assert_sext(s32)
%w0:_(s32) = COPY $w0
%assert_sext:_(s32) = G_ASSERT_SEXT %w0, 8
%sext_inreg:_(s32) = G_SEXT_INREG %assert_sext:_(s32), 12
$w0 = COPY %sext_inreg(s32)
...