derek.holloway
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60 lines
3.3 KiB
LLVM
60 lines
3.3 KiB
LLVM
; RUN: opt -mtriple=aarch64-linux-gnu -mattr=+sve -passes=scalarize-masked-mem-intrin -S < %s | FileCheck %s
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; Testing that masked gathers operating on scalable vectors that are
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; packed in SVE registers are not scalarized.
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; CHECK-LABEL: @masked_gather_nxv4i32(
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; CHECK: call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32
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define <vscale x 4 x i32> @masked_gather_nxv4i32(<vscale x 4 x ptr> %ld, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru) {
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%res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32(<vscale x 4 x ptr> %ld, i32 0, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru)
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ret <vscale x 4 x i32> %res
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}
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; Testing that masked gathers operating on scalable vectors of FP data
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; that is packed in SVE registers are not scalarized.
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; CHECK-LABEL: @masked_gather_nxv2f64(
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; CHECK: call <vscale x 2 x double> @llvm.masked.gather.nxv2f64
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define <vscale x 2 x double> @masked_gather_nxv2f64(<vscale x 2 x ptr> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru) {
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%res = call <vscale x 2 x double> @llvm.masked.gather.nxv2f64(<vscale x 2 x ptr> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru)
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ret <vscale x 2 x double> %res
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}
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; Testing that masked gathers operating on scalable vectors of FP data
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; that is unpacked in SVE registers are not scalarized.
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; CHECK-LABEL: @masked_gather_nxv2f16(
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; CHECK: call <vscale x 2 x half> @llvm.masked.gather.nxv2f16
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define <vscale x 2 x half> @masked_gather_nxv2f16(<vscale x 2 x ptr> %ld, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru) {
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%res = call <vscale x 2 x half> @llvm.masked.gather.nxv2f16(<vscale x 2 x ptr> %ld, i32 0, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru)
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ret <vscale x 2 x half> %res
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}
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; Testing that masked gathers operating on 64-bit fixed vectors are
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; scalarized because NEON doesn't have support for masked gather
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; instructions.
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; CHECK-LABEL: @masked_gather_v2f32(
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; CHECK-NOT: @llvm.masked.gather.v2f32(
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define <2 x float> @masked_gather_v2f32(<2 x ptr> %ld, <2 x i1> %masks, <2 x float> %passthru) {
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%res = call <2 x float> @llvm.masked.gather.v2f32(<2 x ptr> %ld, i32 0, <2 x i1> %masks, <2 x float> %passthru)
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ret <2 x float> %res
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}
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; Testing that masked gathers operating on 128-bit fixed vectors are
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; scalarized because NEON doesn't have support for masked gather
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; instructions and because we are not targeting fixed width SVE.
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; CHECK-LABEL: @masked_gather_v4i32(
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; CHECK-NOT: @llvm.masked.gather.v4i32(
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define <4 x i32> @masked_gather_v4i32(<4 x ptr> %ld, <4 x i1> %masks, <4 x i32> %passthru) {
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%res = call <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ld, i32 0, <4 x i1> %masks, <4 x i32> %passthru)
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ret <4 x i32> %res
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}
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declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32(<vscale x 4 x ptr> %ptrs, i32 %align, <vscale x 4 x i1> %masks, <vscale x 4 x i32> %passthru)
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declare <vscale x 2 x double> @llvm.masked.gather.nxv2f64(<vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks, <vscale x 2 x double> %passthru)
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declare <vscale x 2 x half> @llvm.masked.gather.nxv2f16(<vscale x 2 x ptr> %ptrs, i32 %align, <vscale x 2 x i1> %masks, <vscale x 2 x half> %passthru)
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declare <2 x float> @llvm.masked.gather.v2f32(<2 x ptr> %ptrs, i32 %align, <2 x i1> %masks, <2 x float> %passthru)
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declare <4 x i32> @llvm.masked.gather.v4i32(<4 x ptr> %ptrs, i32 %align, <4 x i1> %masks, <4 x i32> %passthru)
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