derek.holloway
7502bf64a4
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317 lines
14 KiB
YAML
317 lines
14 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I
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# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \
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# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB
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---
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name: abds_i8
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abds_i8
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
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; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
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; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: abds_i8
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; RV32ZBB: liveins: $x10, $x11
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
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; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
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; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
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; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%3:_(s32) = G_ASSERT_SEXT %1, 8
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%4:_(s32) = G_ASSERT_SEXT %2, 8
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%5:_(s8) = G_TRUNC %3(s32)
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%6:_(s8) = G_TRUNC %4(s32)
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%7:_(s8) = G_ABDS %5, %6
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%8:_(s32) = G_ANYEXT %7(s8)
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$x10 = COPY %8(s32)
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PseudoRET implicit $x10
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...
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---
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name: abds_i16
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abds_i16
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
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; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]
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; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: abds_i16
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; RV32ZBB: liveins: $x10, $x11
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
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; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
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; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]
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; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
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; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%3:_(s32) = G_ASSERT_SEXT %1, 16
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%4:_(s32) = G_ASSERT_SEXT %2, 16
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%5:_(s16) = G_TRUNC %3(s32)
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%6:_(s16) = G_TRUNC %4(s32)
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%7:_(s16) = G_ABDS %5, %6
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%8:_(s32) = G_ANYEXT %7(s16)
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$x10 = COPY %8(s32)
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PseudoRET implicit $x10
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...
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---
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name: abds_i32
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abds_i32
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
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; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: abds_i32
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; RV32ZBB: liveins: $x10, $x11
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]]
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; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]
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; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
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; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%3:_(s32) = G_ABDS %1, %2
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$x10 = COPY %3(s32)
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PseudoRET implicit $x10
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...
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---
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name: abds_i64
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: abds_i64
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]
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; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
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; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
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; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
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; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
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; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]
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; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
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; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]
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; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
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; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]
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; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
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; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]
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; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]
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; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]
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; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
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; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
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; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
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%0:_(s32) = COPY $x10
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%1:_(s32) = COPY $x11
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%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = COPY $x10
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%4:_(s32) = COPY $x11
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%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
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%6:_(s64) = G_ABDS %2, %5
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%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
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$x10 = COPY %7(s32)
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$x11 = COPY %8(s32)
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PseudoRET implicit $x10, implicit $x11
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...
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---
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name: abdu_i8
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abdu_i8
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
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; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
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; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: abdu_i8
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; RV32ZBB: liveins: $x10, $x11
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
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; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8
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; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
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; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%3:_(s32) = G_ASSERT_ZEXT %1, 8
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%4:_(s32) = G_ASSERT_ZEXT %2, 8
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%5:_(s8) = G_TRUNC %3(s32)
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%6:_(s8) = G_TRUNC %4(s32)
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%7:_(s8) = G_ABDU %5, %6
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%8:_(s32) = G_ANYEXT %7(s8)
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$x10 = COPY %8(s32)
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PseudoRET implicit $x10
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...
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---
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name: abdu_i16
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abdu_i16
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
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; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]
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; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]
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; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
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; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
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; RV32I-NEXT: PseudoRET implicit $x10
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;
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; RV32ZBB-LABEL: name: abdu_i16
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; RV32ZBB: liveins: $x10, $x11
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; RV32ZBB-NEXT: {{ $}}
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; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
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; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16
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; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]
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; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
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; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
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; RV32ZBB-NEXT: PseudoRET implicit $x10
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%1:_(s32) = COPY $x10
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%2:_(s32) = COPY $x11
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%3:_(s32) = G_ASSERT_ZEXT %1, 16
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%4:_(s32) = G_ASSERT_ZEXT %2, 16
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%5:_(s16) = G_TRUNC %3(s32)
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%6:_(s16) = G_TRUNC %4(s32)
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%7:_(s16) = G_ABDU %5, %6
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%8:_(s32) = G_ANYEXT %7(s16)
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$x10 = COPY %8(s32)
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PseudoRET implicit $x10
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...
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---
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name: abdu_i32
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body: |
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bb.0.entry:
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liveins: $x10, $x11
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; RV32I-LABEL: name: abdu_i32
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; RV32I: liveins: $x10, $x11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
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; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
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|
; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]
|
|
; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]
|
|
; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]
|
|
; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)
|
|
; RV32I-NEXT: PseudoRET implicit $x10
|
|
;
|
|
; RV32ZBB-LABEL: name: abdu_i32
|
|
; RV32ZBB: liveins: $x10, $x11
|
|
; RV32ZBB-NEXT: {{ $}}
|
|
; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
|
|
; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
|
|
; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
|
|
; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]
|
|
; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]
|
|
; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
|
|
; RV32ZBB-NEXT: PseudoRET implicit $x10
|
|
%1:_(s32) = COPY $x10
|
|
%2:_(s32) = COPY $x11
|
|
%3:_(s32) = G_ABDU %1, %2
|
|
$x10 = COPY %3(s32)
|
|
PseudoRET implicit $x10
|
|
...
|
|
---
|
|
name: abdu_i64
|
|
body: |
|
|
bb.0.entry:
|
|
; CHECK-LABEL: name: abdu_i64
|
|
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
|
|
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]
|
|
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]
|
|
; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]
|
|
; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]
|
|
; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]
|
|
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]
|
|
; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]
|
|
; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]
|
|
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]
|
|
; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]
|
|
; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
|
|
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]
|
|
; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]
|
|
; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]
|
|
; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
|
|
; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)
|
|
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
|
|
%0:_(s32) = COPY $x10
|
|
%1:_(s32) = COPY $x11
|
|
%2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
|
|
%3:_(s32) = COPY $x10
|
|
%4:_(s32) = COPY $x11
|
|
%5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
|
|
%6:_(s64) = G_ABDU %2, %5
|
|
%7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
|
|
$x10 = COPY %7(s32)
|
|
$x11 = COPY %8(s32)
|
|
PseudoRET implicit $x10, implicit $x11
|
|
...
|