derek.holloway
7502bf64a4
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38 lines
1.1 KiB
ArmAsm
38 lines
1.1 KiB
ArmAsm
# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+xqcili \
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# RUN: %s -filetype=obj -o - -riscv-add-build-attributes \
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# RUN: | llvm-objdump -dr -M no-aliases - \
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# RUN: | FileCheck %s
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## This tests that we correctly emit relocations for linker relaxation when
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## emitting `QC.E.LI` and `QC.LI`.
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.section .text.ex1, "ax", @progbits
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# CHECK-LABEL: <.text.ex1>:
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blez a1, .L1
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# CHECK-NEXT: bge zero, a1, 0x0 <.text.ex1>
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# CHECK-NEXT: R_RISCV_BRANCH .L1{{$}}
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qc.e.li a0, sym
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# CHECK-NEXT: qc.e.li a0, 0x0
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# CHECK-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
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# CHECK-NEXT: R_RISCV_QC_E_32 sym{{$}}
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# CHECK-NEXT: R_RISCV_RELAX *ABS*{{$}}
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.L1:
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# CHECK: <.L1>:
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ret
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# CHECK-NEXT: c.jr ra
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.section .text.ex2, "ax", @progbits
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# CHECK-LABEL: <.text.ex2>:
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blez a1, .L2
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# CHECK-NEXT: bge zero, a1, 0x0 <.text.ex2>
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# CHECK-NEXT: R_RISCV_BRANCH .L2{{$}}
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qc.li a0, %qc.abs20(sym)
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# CHECK-NEXT: qc.li a0, 0x0
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# CHECK-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
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# CHECK-NEXT: R_RISCV_QC_ABS20_U sym{{$}}
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# CHECK-NEXT: R_RISCV_RELAX *ABS*{{$}}
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.L2:
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# CHECK: <.L2>:
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ret
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# CHECK-NEXT: c.jr ra
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