derek.holloway
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76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
# mach: crisv32
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# output: 40\n40\n140\nabadefb0\n6543789c\n0\n0\n0\n0\n0\n0\n0\n0\n
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; Check for protected operations being NOP in user mode, for the
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; parts implemented in this simulator.
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.include "testutils.inc"
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start
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move 0,ccs
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move 0,usp
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move 0,pid
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move 0,srs
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move 0,ebp
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move 0,spc
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setf u
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; Flag settings, besides what's tested in rfn.ms, rfe.ms and
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; sfe.ms.
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setf i
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move ccs,r3
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dumpr3 ; 0x40
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clearf u
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move ccs,r3
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dumpr3 ; 0x40
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move 0xc0000300,ccs
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move ccs,r3
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dumpr3 ; 0x140
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; R14==USP
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move.d 0xabadefb0,r14
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nop
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nop
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nop
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move usp,r3
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dumpr3 ; 0xabadefb0
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move 0x6543789c,usp
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nop
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nop
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nop
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move.d r14,r3
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dumpr3 ; 0x6543789c
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; We can't go back to kernel mode, so we can't check that R14 in
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; kernel mode wasn't affected.
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; Moves to protected special registers.
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.macro testsr reg,val=-1
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move \val,\reg
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; Registers shorter than dword will not affect the rest of the
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; general register when copied using a move insn.
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clear.d r3
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; Three cycles are needed between move to protected register and
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; read from it, to avoid reading undefined contents due to
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; incomplete forwarding.
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nop
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nop
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move \reg,r3
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dumpr3
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moveq \val,r3
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move r3,\reg
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clear.d r3
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nop
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nop
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move \reg,r3
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dumpr3
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.endm
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testsr pid ; 0 0
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testsr srs,3 ; 0 0
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testsr ebp ; 0 0
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testsr spc ; 0 0
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quit
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