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205 lines
7.0 KiB
YAML
205 lines
7.0 KiB
YAML
# ########################################################################
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# Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights Reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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#
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# ########################################################################
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---
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include: rocsparse_common.yaml
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Definitions:
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- &alpha_beta_range_quick
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- { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 }
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- { alpha: -0.5, beta: 0.5, alphai: -0.5, betai: 1.0 }
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- &alpha_beta_range_checkin
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- { alpha: 2.0, beta: 0.0, alphai: 1.5, betai: 0.5 }
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- { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 }
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- { alpha: 3.0, beta: 1.0, alphai: 2.0, betai: -0.5 }
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- &alpha_beta_range_nightly
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- { alpha: 0.0, beta: 0.0, alphai: 1.5, betai: 0.5 }
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- { alpha: 2.0, beta: 0.67, alphai: 0.0, betai: 1.5 }
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- { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 }
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- { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 }
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Tests:
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- name: csrmv_managed_bad_arg
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category: pre_checkin
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function: csrmv_managed_bad_arg
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precision: *single_double_precisions_complex_real
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- name: csrmv_managed
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category: quick
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function: csrmv_managed
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precision: *single_double_precisions
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M: [10, 300]
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N: [33, 300]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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- name: csrmv_managed
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category: pre_checkin
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function: csrmv_managed
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precision: *single_double_precisions_complex_real
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M: [8, 2000]
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N: [8, 2000]
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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- name: csrmv_managed
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category: nightly
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function: csrmv_managed
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precision: *single_double_precisions_complex_real
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M: [5000]
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N: [5000]
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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- name: csrmv_managed_file
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category: quick
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function: csrmv_managed
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precision: *single_double_precisions
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [mac_econ_fwd500,
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nos2,
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nos4,
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nos6,
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scircuit]
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- name: csrmv_managed_file
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category: pre_checkin
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function: csrmv_managed
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precision: *single_double_precisions
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [nos1,
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nos3,
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nos5,
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nos7]
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- name: csrmv_managed_file
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category: nightly
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function: csrmv_managed
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precision: *single_double_precisions
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [bibd_22_8,
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bmwcra_1,
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amazon0312,
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ASIC_320k,
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sme3Dc,
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shipsec1]
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- name: csrmv_managed_file
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category: quick
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function: csrmv_managed
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precision: *single_only_precisions_complex
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [mplate, qc2534]
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- name: csrmv_managed_file
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category: pre_checkin
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function: csrmv_managed
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precision: *single_double_precisions_complex
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_checkin
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_one]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [Chevron2]
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- name: csrmv_managed_file
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category: nightly
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function: csrmv_managed
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precision: *single_double_precisions_complex
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M: 1
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N: 1
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alpha_beta: *alpha_beta_range_nightly
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero]
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matrix: [rocsparse_matrix_file_rocalution]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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filename: [Chevron3]
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- name: csrmv_managed_graph_test
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category: pre_checkin
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function: csrmv_managed
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precision: *single_double_precisions_complex_real
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M: [10, 500]
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N: [33, 842]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit]
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graph_test: true
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# Regression: csr_adaptive on managed (unified) memory over-read csr_row_ptr
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# past its m+1-length end for the last, partially-filled row block. Benign on
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# discrete GPUs but faults on unified-memory APUs (gfx1151); caught here on any
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# arch under ASAN. Row counts are chosen so the final adaptive row block holds
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# a non-power-of-two number of short rows.
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- name: csrmv_managed_adaptive_last_rowblock
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category: quick
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function: csrmv_managed
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precision: *single_double_precisions
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M: [3, 7, 15, 33, 300]
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N: [3, 7, 15, 33, 300]
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alpha_beta: *alpha_beta_range_quick
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transA: [rocsparse_operation_none]
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baseA: [rocsparse_index_base_zero, rocsparse_index_base_one]
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matrix: [rocsparse_matrix_random]
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spmv_alg: [rocsparse_spmv_alg_csr_adaptive]
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