derek.holloway
7502bf64a4
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275 lines
7.5 KiB
LLVM
275 lines
7.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=aarch64-- -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-- -mattr=+cssc -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-CSSC
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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; auto icmpi64(long x0) { return x0 != 0; }
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define i1 @icmpi64(i64 noundef %0) {
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; CHECK-SD-LABEL: icmpi64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi64:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin x0, x0, #1
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; CHECK-CSSC-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-CSSC-NEXT: ret
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entry:
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%2 = icmp ne i64 %0, 0
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ret i1 %2
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}
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; auto icmpi32(int x0) { return x0 != 0; }
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define i1 @icmpi32(i32 noundef %0) {
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; CHECK-SD-LABEL: icmpi32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi32:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin w0, w0, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%2 = icmp ne i32 %0, 0
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ret i1 %2
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}
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; auto icmpi16(short x0) { return x0 != 0; }
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define i1 @icmpi16(i16 noundef %0) {
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; CHECK-SD-LABEL: icmpi16:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: tst w0, #0xffff
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi16:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: and w8, w0, #0xffff
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; CHECK-CSSC-NEXT: umin w0, w8, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%2 = icmp ne i16 %0, 0
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ret i1 %2
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}
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; auto icmpi8(char x0) { return x0 != 0; }
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define i1 @icmpi8(i8 noundef %0) {
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; CHECK-SD-LABEL: icmpi8:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: tst w0, #0xff
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi8:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: and w8, w0, #0xff
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; CHECK-CSSC-NEXT: umin w0, w8, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%2 = icmp ne i8 %0, 0
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ret i1 %2
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}
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; unsigned long icmpi64i8(char x0) { return x0 != 0; }
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define i64 @icmpi64i8(i8 noundef %0) {
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; CHECK-SD-LABEL: icmpi64i8:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: tst w0, #0xff
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi64i8:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: and w8, w0, #0xff
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; CHECK-CSSC-NEXT: umin w0, w8, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%1 = icmp ne i8 %0, 0
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%2 = zext i1 %1 to i64
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ret i64 %2
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}
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; unsigned long setcc_i8_i64(char x0) { return x0 != 0; }
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define i8 @setcc_i8_i64(i64 %x) {
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; CHECK-SD-LABEL: setcc_i8_i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: setcc_i8_i64:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin x0, x0, #1
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; CHECK-CSSC-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-CSSC-NEXT: ret
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entry:
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%cmp = icmp ne i64 %x, 0
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%conv = zext i1 %cmp to i8
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ret i8 %conv
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}
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; short setcc_i16_i32(int x0) { return x0 != 0; }
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define i16 @setcc_i16_i32(i32 %x) {
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; CHECK-SD-LABEL: setcc_i16_i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: setcc_i16_i32:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin w0, w0, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%cmp = icmp ne i32 %x, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; int setcc_i32_i64(unsigned long x0) { return x0 != 0; }
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define i32 @setcc_i32_i64(i64 %x) {
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; CHECK-SD-LABEL: setcc_i32_i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: setcc_i32_i64:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin x0, x0, #1
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; CHECK-CSSC-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-CSSC-NEXT: ret
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entry:
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%cmp = icmp ne i64 %x, 0
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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; unsigned long setcc_i64_i64(unsigned long x0) { return x0 != 0; }
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define i64 @setcc_i64_i64(i64 %x) {
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; CHECK-SD-LABEL: setcc_i64_i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: setcc_i64_i64:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: umin x0, x0, #1
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; CHECK-CSSC-NEXT: ret
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entry:
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%cmp = icmp ne i64 %x, 0
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%conv = zext i1 %cmp to i64
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ret i64 %conv
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}
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define <2 x i1> @setcc_v2i1_v2i64(<2 x i64> %x) {
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; CHECK-LABEL: setcc_v2i1_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.2d, v0.2d, v0.2d
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <2 x i64> %x, zeroinitializer
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ret <2 x i1> %cmp
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}
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define <4 x i1> @setcc_v4i1_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: setcc_v4i1_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <4 x i32> %x, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <8 x i1> @setcc_v8i1_v8i16(<8 x i16> %x) {
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; CHECK-LABEL: setcc_v8i1_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <8 x i16> %x, zeroinitializer
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ret <8 x i1> %cmp
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}
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define <16 x i1> @setcc_v16i1_v16i8(<16 x i8> %x) {
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; CHECK-LABEL: setcc_v16i1_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.16b, v0.16b, v0.16b
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <16 x i8> %x, zeroinitializer
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ret <16 x i1> %cmp
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}
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define <2 x i8> @setcc_v2i8_v2i64(<2 x i64> %x) {
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; CHECK-LABEL: setcc_v2i8_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.2d, v0.2d, v0.2d
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; CHECK-NEXT: movi v1.2s, #1
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <2 x i64> %x, zeroinitializer
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%conv = zext <2 x i1> %cmp to <2 x i8>
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ret <2 x i8> %conv
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}
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define <4 x i16> @setcc_v4i16_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: setcc_v4i16_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: movi v1.4h, #1
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <4 x i32> %x, zeroinitializer
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%conv = zext <4 x i1> %cmp to <4 x i16>
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ret <4 x i16> %conv
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}
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define <4 x i32> @setcc_v4i32_v4i32(<4 x i32> %x) {
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; CHECK-LABEL: setcc_v4i32_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ne <4 x i32> %x, zeroinitializer
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%conv = zext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %conv
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}
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; auto icmpi128(int128 x0) { return x0 != 0; }
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define i1 @icmpi128(i128 noundef %0) {
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; CHECK-SD-LABEL: icmpi128:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: orr x8, x0, x1
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; CHECK-SD-NEXT: cmp x8, #0
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-CSSC-LABEL: icmpi128:
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; CHECK-CSSC: // %bb.0: // %entry
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; CHECK-CSSC-NEXT: orr x8, x0, x1
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; CHECK-CSSC-NEXT: umin x0, x8, #1
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; CHECK-CSSC-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-CSSC-NEXT: ret
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entry:
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%2 = icmp ne i128 %0, 0
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ret i1 %2
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}
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