derek.holloway
7502bf64a4
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30 lines
1.5 KiB
LLVM
30 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9
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; Marking the image loads as invariant should allow both loads to be hoisted
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; above both stores.
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define amdgpu_ps void @test(<8 x i32> inreg %load, <8 x i32> inreg %store) {
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; GFX9-LABEL: test:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v1, 1
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; GFX9-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
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; GFX9-NEXT: image_load v3, v1, s[0:7] dmask:0x1 unorm
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; GFX9-NEXT: s_waitcnt vmcnt(1)
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; GFX9-NEXT: image_store v2, v0, s[8:15] dmask:0x1 unorm
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; GFX9-NEXT: s_waitcnt vmcnt(1)
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; GFX9-NEXT: image_store v3, v1, s[8:15] dmask:0x1 unorm
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; GFX9-NEXT: s_endpgm
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%data0 = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 1, i32 0, <8 x i32> %load, i32 0, i32 0), !invariant.load !0
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call void @llvm.amdgcn.image.store.1d.f32.i32(float %data0, i32 1, i32 0, <8 x i32> %store, i32 0, i32 0)
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%data1 = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 1, i32 1, <8 x i32> %load, i32 0, i32 0), !invariant.load !0
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call void @llvm.amdgcn.image.store.1d.f32.i32(float %data1, i32 1, i32 1, <8 x i32> %store, i32 0, i32 0)
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ret void
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}
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declare float @llvm.amdgcn.image.load.1d.f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg)
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declare void @llvm.amdgcn.image.store.1d.f32.i32(float, i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg)
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!0 = !{}
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