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97 lines
3.4 KiB
LLVM
97 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.lds.kernel.id()
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declare i32 @llvm.amdgcn.workgroup.id.x()
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define void @function_lds_id(ptr addrspace(1) %out) {
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; GCN-LABEL: function_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_add_i32 s4, s15, s12
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; GCN-NEXT: v_mov_b32_e32 v2, s4
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%tmp0 = call i32 @llvm.amdgcn.lds.kernel.id()
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%help = call i32 @llvm.amdgcn.workgroup.id.x()
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%both = add i32 %tmp0, %help
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store i32 %both, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @kernel_lds_id(ptr addrspace(1) %out) !llvm.amdgcn.lds.kernel.id !0 {
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; GCN-LABEL: kernel_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GCN-NEXT: s_add_i32 s2, s14, 42
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; GCN-NEXT: v_mov_b32_e32 v2, s2
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_endpgm
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%tmp0 = call i32 @llvm.amdgcn.lds.kernel.id()
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%help = call i32 @llvm.amdgcn.workgroup.id.x()
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%both = add i32 %tmp0, %help
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store i32 %both, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @indirect_lds_id(ptr addrspace(1) %out) !llvm.amdgcn.lds.kernel.id !1 {
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; GCN-LABEL: indirect_lds_id:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_mov_b32 s32, 0
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_add_u32 s0, s0, s17
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: s_mov_b32 s13, s15
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; GCN-NEXT: s_mov_b32 s12, s14
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; GCN-NEXT: s_load_dwordx2 s[18:19], s[8:9], 0x0
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; GCN-NEXT: s_add_u32 s8, s8, 8
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; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
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; GCN-NEXT: s_addc_u32 s9, s9, 0
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; GCN-NEXT: s_getpc_b64 s[14:15]
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; GCN-NEXT: s_add_u32 s14, s14, function_lds_id@gotpcrel32@lo+4
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; GCN-NEXT: s_addc_u32 s15, s15, function_lds_id@gotpcrel32@hi+12
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; GCN-NEXT: s_load_dwordx2 s[20:21], s[14:15], 0x0
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; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
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; GCN-NEXT: v_or_b32_e32 v0, v0, v1
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; GCN-NEXT: v_or_b32_e32 v31, v0, v2
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; GCN-NEXT: s_mov_b32 s15, 21
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; GCN-NEXT: s_mov_b32 s14, s16
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s18
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; GCN-NEXT: v_mov_b32_e32 v1, s19
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; GCN-NEXT: s_swappc_b64 s[30:31], s[20:21]
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; GCN-NEXT: s_endpgm
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call void @function_lds_id(ptr addrspace(1) %out)
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ret void
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}
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define amdgpu_kernel void @doesnt_use_it(ptr addrspace(1) %out) !llvm.amdgcn.lds.kernel.id !0 {
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; GCN-LABEL: doesnt_use_it:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_mov_b32 flat_scratch_lo, s13
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; GCN-NEXT: s_add_i32 s12, s12, s17
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; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0
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; GCN-NEXT: v_mov_b32_e32 v2, 0x64
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: v_mov_b32_e32 v1, s1
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; GCN-NEXT: flat_store_dword v[0:1], v2
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; GCN-NEXT: s_endpgm
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store i32 100, ptr addrspace(1) %out
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ret void
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}
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!0 = !{i32 42}
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!1 = !{i32 21}
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