TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s

define float @v_log_f32(float %src)  {
; GCN-LABEL: v_log_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f32_e32 v0, v0
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %log = call float @llvm.amdgcn.log.f32(float %src)
  ret float %log
}

define float @v_fabs_log_f32(float %src)  {
; GCN-LABEL: v_fabs_log_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f32_e64 v0, |v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call float @llvm.fabs.f32(float %src)
  %log = call float @llvm.amdgcn.log.f32(float %fabs.src)
  ret float %log
}

define float @v_fneg_fabs_log_f32(float %src)  {
; GCN-LABEL: v_fneg_fabs_log_f32:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f32_e64 v0, -|v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call float @llvm.fabs.f32(float %src)
  %neg.fabs.src = fneg float %fabs.src
  %log = call float @llvm.amdgcn.log.f32(float %neg.fabs.src)
  ret float %log
}

define half @v_log_f16(half %src)  {
; GCN-LABEL: v_log_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f16_e32 v0, v0
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %log = call half @llvm.amdgcn.log.f16(half %src)
  ret half %log
}

define half @v_fabs_log_f16(half %src)  {
; GCN-LABEL: v_fabs_log_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f16_e64 v0, |v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call half @llvm.fabs.f16(half %src)
  %log = call half @llvm.amdgcn.log.f16(half %fabs.src)
  ret half %log
}

define half @v_fneg_fabs_log_f16(half %src)  {
; GCN-LABEL: v_fneg_fabs_log_f16:
; GCN:       ; %bb.0:
; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT:    v_log_f16_e64 v0, -|v0|
; GCN-NEXT:    s_setpc_b64 s[30:31]
  %fabs.src = call half @llvm.fabs.f16(half %src)
  %neg.fabs.src = fneg half %fabs.src
  %log = call half @llvm.amdgcn.log.f16(half %neg.fabs.src)
  ret half %log
}

declare half @llvm.amdgcn.log.f16(half) #0
declare float @llvm.amdgcn.log.f32(float) #0
declare float @llvm.fabs.f32(float) #0
declare half @llvm.fabs.f16(half) #0

attributes #0 = { nounwind readnone speculatable willreturn }