derek.holloway
7502bf64a4
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290 lines
14 KiB
LLVM
290 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GCN,GFX908,GFX908-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck --check-prefixes=GCN,GFX908,GFX908-GISEL %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug < %s | FileCheck --check-prefixes=GCN,GFX908,GFX908-SDAG %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx908 -mattr=-mfma-inline-literal-bug < %s | FileCheck --check-prefixes=GCN,GFX908,GFX908-GISEL %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-vgpr-form=0 < %s | FileCheck --check-prefixes=GCN,GFX90A %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck --check-prefixes=GCN,GFX90A-VGPR %s
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declare <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32, i32, <16 x i32>, i32, i32, i32)
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declare <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32, i32, <4 x i32>, i32, i32, i32)
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define amdgpu_kernel void @test_mfma_i32_32x32x8i8(ptr addrspace(1) %arg) #0 {
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; GFX908-SDAG-LABEL: test_mfma_i32_32x32x8i8:
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; GFX908-SDAG: ; %bb.0: ; %bb
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; GFX908-SDAG-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v0, 1
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v16, 0
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; GFX908-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-SDAG-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GFX908-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s0
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, s1
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v2, s2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a0, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s3
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a1, v1
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a2, v2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a3, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, s4
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v2, s5
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s6
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a4, v1
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a5, v2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a6, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, s7
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v2, s8
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s9
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a7, v1
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a8, v2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a9, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, s10
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v2, s11
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s12
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a10, v1
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a11, v2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a12, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, s13
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v2, s14
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v17, s15
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a13, v1
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a14, v2
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; GFX908-SDAG-NEXT: v_accvgpr_write_b32 a15, v17
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; GFX908-SDAG-NEXT: v_mov_b32_e32 v1, 2
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; GFX908-SDAG-NEXT: s_nop 1
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; GFX908-SDAG-NEXT: v_mfma_i32_32x32x8i8 a[0:15], v0, v1, a[0:15] cbsz:1 abid:2 blgp:3
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; GFX908-SDAG-NEXT: s_nop 15
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; GFX908-SDAG-NEXT: s_nop 1
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v15, a15
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v14, a14
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v13, a13
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v12, a12
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v3, a3
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v2, a2
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v1, a1
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v0, a0
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v7, a7
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v6, a6
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v5, a5
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v4, a4
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v11, a11
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v10, a10
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v9, a9
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; GFX908-SDAG-NEXT: v_accvgpr_read_b32 v8, a8
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; GFX908-SDAG-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
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; GFX908-SDAG-NEXT: s_nop 0
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; GFX908-SDAG-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
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; GFX908-SDAG-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
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; GFX908-SDAG-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
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; GFX908-SDAG-NEXT: s_endpgm
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;
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; GFX908-GISEL-LABEL: test_mfma_i32_32x32x8i8:
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; GFX908-GISEL: ; %bb.0: ; %bb
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; GFX908-GISEL-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v0, 1
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v16, 0
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; GFX908-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-GISEL-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GFX908-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s0
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, s1
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a0, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s3
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a1, v1
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a2, v2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a3, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, s4
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s5
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s6
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a4, v1
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a5, v2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a6, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, s7
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s8
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s9
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a7, v1
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a8, v2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a9, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, s10
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s11
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s12
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a10, v1
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a11, v2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a12, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, s13
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v2, s14
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v17, s15
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a13, v1
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a14, v2
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; GFX908-GISEL-NEXT: v_accvgpr_write_b32 a15, v17
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; GFX908-GISEL-NEXT: v_mov_b32_e32 v1, 2
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; GFX908-GISEL-NEXT: s_nop 1
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; GFX908-GISEL-NEXT: v_mfma_i32_32x32x8i8 a[0:15], v0, v1, a[0:15] cbsz:1 abid:2 blgp:3
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; GFX908-GISEL-NEXT: s_nop 15
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; GFX908-GISEL-NEXT: s_nop 1
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v0, a0
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v1, a1
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v2, a2
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v3, a3
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v4, a4
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v5, a5
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v6, a6
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v7, a7
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v8, a8
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v9, a9
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v10, a10
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v11, a11
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v12, a12
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v13, a13
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v14, a14
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; GFX908-GISEL-NEXT: v_accvgpr_read_b32 v15, a15
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; GFX908-GISEL-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
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; GFX908-GISEL-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
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; GFX908-GISEL-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
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; GFX908-GISEL-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
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; GFX908-GISEL-NEXT: s_endpgm
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;
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; GFX90A-LABEL: test_mfma_i32_32x32x8i8:
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; GFX90A: ; %bb.0: ; %bb
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; GFX90A-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GFX90A-NEXT: v_mov_b32_e32 v0, 1
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; GFX90A-NEXT: v_mov_b32_e32 v1, 2
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: v_accvgpr_write_b32 a0, s0
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; GFX90A-NEXT: v_accvgpr_write_b32 a1, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a2, s2
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; GFX90A-NEXT: v_accvgpr_write_b32 a3, s3
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; GFX90A-NEXT: v_accvgpr_write_b32 a4, s4
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; GFX90A-NEXT: v_accvgpr_write_b32 a5, s5
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; GFX90A-NEXT: v_accvgpr_write_b32 a6, s6
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; GFX90A-NEXT: v_accvgpr_write_b32 a7, s7
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; GFX90A-NEXT: v_accvgpr_write_b32 a8, s8
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; GFX90A-NEXT: v_accvgpr_write_b32 a9, s9
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; GFX90A-NEXT: v_accvgpr_write_b32 a10, s10
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; GFX90A-NEXT: v_accvgpr_write_b32 a11, s11
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; GFX90A-NEXT: v_accvgpr_write_b32 a12, s12
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; GFX90A-NEXT: v_accvgpr_write_b32 a13, s13
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; GFX90A-NEXT: v_accvgpr_write_b32 a14, s14
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; GFX90A-NEXT: v_accvgpr_write_b32 a15, s15
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; GFX90A-NEXT: s_nop 1
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; GFX90A-NEXT: v_mfma_i32_32x32x8i8 a[0:15], v0, v1, a[0:15] cbsz:1 abid:2 blgp:3
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; GFX90A-NEXT: v_mov_b32_e32 v0, 0
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; GFX90A-NEXT: s_nop 15
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; GFX90A-NEXT: s_nop 1
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; GFX90A-NEXT: global_store_dwordx4 v0, a[12:15], s[16:17] offset:48
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; GFX90A-NEXT: global_store_dwordx4 v0, a[8:11], s[16:17] offset:32
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; GFX90A-NEXT: global_store_dwordx4 v0, a[4:7], s[16:17] offset:16
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; GFX90A-NEXT: global_store_dwordx4 v0, a[0:3], s[16:17]
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; GFX90A-NEXT: s_endpgm
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;
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; GFX90A-VGPR-LABEL: test_mfma_i32_32x32x8i8:
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; GFX90A-VGPR: ; %bb.0: ; %bb
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; GFX90A-VGPR-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x24
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; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 1
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; GFX90A-VGPR-NEXT: v_mov_b32_e32 v17, 2
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; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-VGPR-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
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; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[4:5], s[4:5], s[4:5] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[6:7], s[6:7], s[6:7] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[8:9], s[8:9], s[8:9] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[10:11], s[10:11], s[10:11] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[12:13], s[12:13], s[12:13] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[14:15], s[14:15], s[14:15] op_sel:[0,1]
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; GFX90A-VGPR-NEXT: s_nop 1
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; GFX90A-VGPR-NEXT: v_mfma_i32_32x32x8i8 v[0:15], v16, v17, v[0:15] cbsz:1 abid:2 blgp:3
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; GFX90A-VGPR-NEXT: v_mov_b32_e32 v16, 0
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; GFX90A-VGPR-NEXT: s_nop 15
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; GFX90A-VGPR-NEXT: s_nop 1
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; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[12:15], s[16:17] offset:48
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; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[8:11], s[16:17] offset:32
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; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[4:7], s[16:17] offset:16
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; GFX90A-VGPR-NEXT: global_store_dwordx4 v16, v[0:3], s[16:17]
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; GFX90A-VGPR-NEXT: s_endpgm
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bb:
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%in.1 = load <16 x i32>, ptr addrspace(1) %arg
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%mai.1 = tail call <16 x i32> @llvm.amdgcn.mfma.i32.32x32x8i8(i32 1, i32 2, <16 x i32> %in.1, i32 1, i32 2, i32 3)
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store <16 x i32> %mai.1, ptr addrspace(1) %arg
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ret void
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}
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define amdgpu_kernel void @test_mfma_i32_16x16x16i8(ptr addrspace(1) %arg) #0 {
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; GFX908-LABEL: test_mfma_i32_16x16x16i8:
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; GFX908: ; %bb.0: ; %bb
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; GFX908-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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; GFX908-NEXT: v_mov_b32_e32 v0, 1
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; GFX908-NEXT: v_mov_b32_e32 v1, 2
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; GFX908-NEXT: v_mov_b32_e32 v4, 0
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; GFX908-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
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; GFX908-NEXT: s_waitcnt lgkmcnt(0)
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; GFX908-NEXT: v_mov_b32_e32 v5, s0
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; GFX908-NEXT: v_mov_b32_e32 v2, s1
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; GFX908-NEXT: v_mov_b32_e32 v3, s2
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; GFX908-NEXT: v_accvgpr_write_b32 a0, v5
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; GFX908-NEXT: v_mov_b32_e32 v5, s3
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; GFX908-NEXT: v_accvgpr_write_b32 a1, v2
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; GFX908-NEXT: v_accvgpr_write_b32 a2, v3
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; GFX908-NEXT: v_accvgpr_write_b32 a3, v5
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; GFX908-NEXT: s_nop 0
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; GFX908-NEXT: v_mfma_i32_16x16x16i8 a[0:3], v0, v1, a[0:3] cbsz:1 abid:2 blgp:3
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; GFX908-NEXT: s_nop 9
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; GFX908-NEXT: v_accvgpr_read_b32 v0, a0
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; GFX908-NEXT: v_accvgpr_read_b32 v1, a1
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; GFX908-NEXT: v_accvgpr_read_b32 v2, a2
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; GFX908-NEXT: v_accvgpr_read_b32 v3, a3
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; GFX908-NEXT: s_nop 1
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; GFX908-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
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; GFX908-NEXT: s_endpgm
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;
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; GFX90A-LABEL: test_mfma_i32_16x16x16i8:
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; GFX90A: ; %bb.0: ; %bb
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; GFX90A-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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; GFX90A-NEXT: v_mov_b32_e32 v0, 1
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; GFX90A-NEXT: v_mov_b32_e32 v2, 2
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; GFX90A-NEXT: v_mov_b32_e32 v1, 0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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|
; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
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; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
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; GFX90A-NEXT: v_accvgpr_write_b32 a0, s0
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; GFX90A-NEXT: v_accvgpr_write_b32 a1, s1
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; GFX90A-NEXT: v_accvgpr_write_b32 a2, s2
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; GFX90A-NEXT: v_accvgpr_write_b32 a3, s3
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; GFX90A-NEXT: s_nop 1
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; GFX90A-NEXT: v_mfma_i32_16x16x16i8 a[0:3], v0, v2, a[0:3] cbsz:1 abid:2 blgp:3
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; GFX90A-NEXT: s_nop 10
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|
; GFX90A-NEXT: global_store_dwordx4 v1, a[0:3], s[6:7]
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; GFX90A-NEXT: s_endpgm
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|
;
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; GFX90A-VGPR-LABEL: test_mfma_i32_16x16x16i8:
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; GFX90A-VGPR: ; %bb.0: ; %bb
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|
; GFX90A-VGPR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
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|
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v4, 1
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|
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v6, 2
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|
; GFX90A-VGPR-NEXT: v_mov_b32_e32 v5, 0
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|
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
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|
; GFX90A-VGPR-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0
|
|
; GFX90A-VGPR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[0:1], s[0:1], s[0:1] op_sel:[0,1]
|
|
; GFX90A-VGPR-NEXT: v_pk_mov_b32 v[2:3], s[2:3], s[2:3] op_sel:[0,1]
|
|
; GFX90A-VGPR-NEXT: s_nop 1
|
|
; GFX90A-VGPR-NEXT: v_mfma_i32_16x16x16i8 v[0:3], v4, v6, v[0:3] cbsz:1 abid:2 blgp:3
|
|
; GFX90A-VGPR-NEXT: s_nop 10
|
|
; GFX90A-VGPR-NEXT: global_store_dwordx4 v5, v[0:3], s[6:7]
|
|
; GFX90A-VGPR-NEXT: s_endpgm
|
|
bb:
|
|
%in.1 = load <4 x i32>, ptr addrspace(1) %arg
|
|
%mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.16x16x16i8(i32 1, i32 2, <4 x i32> %in.1, i32 1, i32 2, i32 3)
|
|
store <4 x i32> %mai.1, ptr addrspace(1) %arg
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "amdgpu-flat-work-group-size"="1,256" }
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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|
; GCN: {{.*}}
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