derek.holloway
7502bf64a4
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43 lines
1.9 KiB
LLVM
43 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck %s --check-prefixes=GCN,GFX906
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; RUN: llc -mtriple=amdgcn -mcpu=gfx908 < %s | FileCheck %s --check-prefixes=GCN,GFX908
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck %s --check-prefixes=GCN,GFX10
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declare i32 @llvm.amdgcn.sdot2(<2 x i16> %a, <2 x i16> %b, i32 %c, i1 %clamp)
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_clamp
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; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX908: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} clamp{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot2_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x i16>, ptr addrspace(1) %a
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%b.val = load <2 x i16>, ptr addrspace(1) %b
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 1)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot2_no_clamp
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; GFX906: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX908: v_dot2c_i32_i16_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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; GFX10: v_dot2_i32_i16 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}{{$}}
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define amdgpu_kernel void @test_llvm_amdgcn_sdot2_no_clamp(
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x i16>, ptr addrspace(1) %a
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%b.val = load <2 x i16>, ptr addrspace(1) %b
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%c.val = load i32, ptr addrspace(1) %c
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%r.val = call i32 @llvm.amdgcn.sdot2(<2 x i16> %a.val, <2 x i16> %b.val, i32 %c.val, i1 0)
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store i32 %r.val, ptr addrspace(1) %r
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ret void
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}
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