derek.holloway
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214 lines
8.0 KiB
YAML
214 lines
8.0 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra -o - %s | FileCheck %s
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# Cannot fold this without moving the def of %7 after the and.
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---
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name: no_fold_andn2_select_condition_live_out_phi
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec
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; CHECK-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]].sub0
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; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %3:vgpr_32, [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store (s64), addrspace 3)
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; CHECK-NEXT: ATOMIC_FENCE 4, 2
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
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; CHECK-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.2
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%7:sreg_64_xexec = S_MOV_B64 -1
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undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM 0
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bb.2:
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successors: %bb.1, %bb.2
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%4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %7, implicit $exec
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V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec
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%5.sub1:vreg_64 = COPY %5.sub0
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DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
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ATOMIC_FENCE 4, 2
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%7:sreg_64_xexec = S_MOV_B64 0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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S_BRANCH %bb.2
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...
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# It's OK to fold this, since the phi def is after the andn2 insert point.
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---
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name: fold_andn2_select_condition_live_out_phi_reorder
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_reorder
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]].sub0
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; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %3:vgpr_32, [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store (s64), addrspace 3)
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; CHECK-NEXT: ATOMIC_FENCE 4, 2
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; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.2
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%7:sreg_64_xexec = S_MOV_B64 -1
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undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM 0
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bb.2:
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successors: %bb.1, %bb.2
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%4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %7, implicit $exec
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V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec
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%5.sub1:vreg_64 = COPY %5.sub0
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DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
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ATOMIC_FENCE 4, 2
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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%7:sreg_64_xexec = S_MOV_B64 0
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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S_BRANCH %bb.2
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...
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---
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name: no_fold_andn2_select_condition_live_out_phi_physreg
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: no_fold_andn2_select_condition_live_out_phi_physreg
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 -1
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $sgpr4_sgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec
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; CHECK-NEXT: V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]].sub0
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; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %2:vgpr_32, [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store (s64), addrspace 3)
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; CHECK-NEXT: ATOMIC_FENCE 4, 2
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; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 0
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; CHECK-NEXT: $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.2
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$sgpr4_sgpr5 = S_MOV_B64 -1
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undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM 0
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bb.2:
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successors: %bb.1, %bb.2
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liveins: $sgpr4_sgpr5
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%4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec
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V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec
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%5.sub1:vreg_64 = COPY %5.sub0
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DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
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ATOMIC_FENCE 4, 2
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$sgpr4_sgpr5 = S_MOV_B64 0
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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S_BRANCH %bb.2
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...
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---
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name: fold_andn2_select_condition_live_out_phi_physreg_reorder
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fold_andn2_select_condition_live_out_phi_physreg_reorder
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 -1
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; CHECK-NEXT: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: S_ENDPGM 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $sgpr4_sgpr5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_64 = COPY [[V_MOV_B32_e32_]].sub0
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; CHECK-NEXT: DS_WRITE_B64_gfx9 undef %2:vgpr_32, [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store (s64), addrspace 3)
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; CHECK-NEXT: ATOMIC_FENCE 4, 2
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; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, $sgpr4_sgpr5, implicit-def dead $scc
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; CHECK-NEXT: $sgpr4_sgpr5 = S_MOV_B64 0
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; CHECK-NEXT: S_BRANCH %bb.2
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bb.0:
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successors: %bb.2
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$sgpr4_sgpr5 = S_MOV_B64 -1
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undef %5.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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S_ENDPGM 0
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bb.2:
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successors: %bb.1, %bb.2
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liveins: $sgpr4_sgpr5
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%4:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, $sgpr4_sgpr5, implicit $exec
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V_CMP_NE_U32_e32 1, %4, implicit-def $vcc, implicit $exec
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%5.sub1:vreg_64 = COPY %5.sub0
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DS_WRITE_B64_gfx9 undef %6:vgpr_32, %5, 0, 0, implicit $exec :: (store (s64), addrspace 3)
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ATOMIC_FENCE 4, 2
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$vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
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$sgpr4_sgpr5 = S_MOV_B64 0
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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S_BRANCH %bb.2
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...
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