derek.holloway
7502bf64a4
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59 lines
2.2 KiB
LLVM
59 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=r600 -mcpu=redwood -disable-promote-alloca-to-vector -disable-promote-alloca-to-lds < %s | FileCheck %s
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;
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; CFG flattening should use parallel-and mode to generate branch conditions and
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; then merge if-regions with the same bodies.
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;
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; CHECK: AND_INT
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; CHECK-NEXT: AND_INT
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; CHECK-NEXT: OR_INT
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; FIXME: For some reason having the allocas here allowed the flatten cfg pass
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; to do its transformation, however now that we are using local memory for
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; allocas, the transformation isn't happening.
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define amdgpu_kernel void @_Z9chk1D_512v() #0 {
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entry:
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%a0 = alloca i32, align 4, addrspace(5)
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%b0 = alloca i32, align 4, addrspace(5)
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%c0 = alloca i32, align 4, addrspace(5)
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%d0 = alloca i32, align 4, addrspace(5)
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%a1 = alloca i32, align 4, addrspace(5)
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%b1 = alloca i32, align 4, addrspace(5)
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%c1 = alloca i32, align 4, addrspace(5)
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%d1 = alloca i32, align 4, addrspace(5)
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%data = alloca i32, align 4, addrspace(5)
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%0 = load i32, ptr addrspace(5) %a0, align 4
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%1 = load i32, ptr addrspace(5) %b0, align 4
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%cmp = icmp ne i32 %0, %1
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br i1 %cmp, label %land.lhs.true, label %if.end
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land.lhs.true: ; preds = %entry
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%2 = load i32, ptr addrspace(5) %c0, align 4
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%3 = load i32, ptr addrspace(5) %d0, align 4
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%cmp1 = icmp ne i32 %2, %3
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %land.lhs.true
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store i32 1, ptr addrspace(5) %data, align 4
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br label %if.end
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if.end: ; preds = %if.then, %land.lhs.true, %entry
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%4 = load i32, ptr addrspace(5) %a1, align 4
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%5 = load i32, ptr addrspace(5) %b1, align 4
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%cmp2 = icmp ne i32 %4, %5
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br i1 %cmp2, label %land.lhs.true3, label %if.end6
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land.lhs.true3: ; preds = %if.end
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%6 = load i32, ptr addrspace(5) %c1, align 4
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%7 = load i32, ptr addrspace(5) %d1, align 4
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%cmp4 = icmp ne i32 %6, %7
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br i1 %cmp4, label %if.then5, label %if.end6
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if.then5: ; preds = %land.lhs.true3
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store i32 1, ptr addrspace(5) %data, align 4
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br label %if.end6
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if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end
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ret void
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}
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