derek.holloway
7502bf64a4
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44 lines
1.8 KiB
LLVM
44 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
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; CHECK-LABEL: main:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: CALL_FS
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; CHECK-NEXT: ALU 7, @4, KC0[], KC1[]
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; CHECK-NEXT: EXPORT T0.X___
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; CHECK-NEXT: CF_END
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; CHECK-NEXT: ALU clause starting at 4:
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; CHECK-NEXT: MULADD_IEEE T0.X, T0.W, T0.W, literal.x,
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; CHECK-NEXT: MULADD_IEEE T0.Y, T1.W, T1.W, literal.x, BS:VEC_120/SCL_212
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; CHECK-NEXT: MULADD_IEEE * T0.Z, T2.W, T2.W, literal.x, BS:VEC_201
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; CHECK-NEXT: 1073741824(2.000000e+00), 0(0.000000e+00)
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; CHECK-NEXT: DOT4 T0.X, T0.X, T0.X,
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; CHECK-NEXT: DOT4 T0.Y (MASKED), T0.Y, T0.Y,
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; CHECK-NEXT: DOT4 T0.Z (MASKED), T0.Z, T0.Z,
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; CHECK-NEXT: DOT4 * T0.W (MASKED), T0.W, T0.W,
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%w0 = extractelement <4 x float> %reg0, i32 3
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%w1 = extractelement <4 x float> %reg1, i32 3
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%w2 = extractelement <4 x float> %reg2, i32 3
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%sq0 = fmul float %w0, %w0
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%r0 = fadd float %sq0, 2.0
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%sq1 = fmul float %w1, %w1
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%r1 = fadd float %sq1, 2.0
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%sq2 = fmul float %w2, %w2
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%r2 = fadd float %sq2, 2.0
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%v0 = insertelement <4 x float> poison, float %r0, i32 0
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%v1 = insertelement <4 x float> %v0, float %r1, i32 1
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%v2 = insertelement <4 x float> %v1, float %r2, i32 2
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%res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2)
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%vecres = insertelement <4 x float> poison, float %res, i32 0
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call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2)
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ret void
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}
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; Function Attrs: readnone
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declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1
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declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
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attributes #1 = { readnone }
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