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80 lines
3.1 KiB
YAML
80 lines
3.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=armv7-apple-ios -run-pass=regallocfast -o - %s | FileCheck %s
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# RUN: llc -mtriple=armv7-apple-ios -passes=regallocfast -o - %s | FileCheck %s
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# tBX_RET uses an implicit vreg with a sub-register. That implicit use will
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# typically be rewritten as a use of the relevant super-register. Make sure
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# regallocfast is able to process the remaining operands (here, %2) and rewrite
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# them to use physical registers.
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---
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name: different_vreg
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d2, $d4, $d7
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; CHECK-LABEL: name: different_vreg
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; CHECK: liveins: $d2, $d4, $d7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $d5 = COPY killed $d4
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; CHECK-NEXT: renamable $d4 = COPY killed $d2
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; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q1
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; CHECK-NEXT: renamable $d1 = COPY renamable $d4
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; CHECK-NEXT: renamable $d2 = COPY killed renamable $d5
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; CHECK-NEXT: renamable $d3 = COPY killed renamable $d4
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; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit killed renamable $d7, implicit killed $q0_q1
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%0:dpr_vfp2 = COPY $d4
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%1:dpr_vfp2 = COPY $d2
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%2:dpr_vfp2 = COPY $d7
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undef %4.dsub_0:dquad = COPY %0
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%4.dsub_1:dquad = COPY %1
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%4.dsub_2:dquad = COPY %0
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%4.dsub_3:dquad = COPY %1
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tBX_RET 14, $noreg, implicit %4.dsub_3, implicit %2
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...
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# tBX_RET uses the same vreg twice, make sure regallocfast is able to allocate a
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# physical register for it and replace both references.
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---
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name: same_vreg_twice
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d2, $d4
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; CHECK-LABEL: name: same_vreg_twice
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; CHECK: liveins: $d2, $d4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $d5 = COPY killed $d4
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; CHECK-NEXT: renamable $d4 = COPY killed $d2
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; CHECK-NEXT: undef renamable $d0 = COPY renamable $d5, implicit-def $q0_q1
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; CHECK-NEXT: renamable $d1 = COPY renamable $d4
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; CHECK-NEXT: renamable $d2 = COPY killed renamable $d5
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; CHECK-NEXT: renamable $d3 = COPY killed renamable $d4
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; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit renamable $d3, implicit killed $q0_q1
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%0:dpr_vfp2 = COPY $d4
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%1:dpr_vfp2 = COPY $d2
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undef %4.dsub_0:dquad = COPY %0
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%4.dsub_1:dquad = COPY %1
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%4.dsub_2:dquad = COPY %0
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%4.dsub_3:dquad = COPY %1
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tBX_RET 14, $noreg, implicit %4.dsub_1, implicit %4.dsub_3
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...
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# tBL partially defines two vregs, which turn out to be dead. Make sure
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# regallocfast allocates a phys reg for both %0 and %1.
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---
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name: partial_dead
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: partial_dead
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; CHECK: tBL 14 /* CC::al */, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $q0_q1, implicit-def dead $q2_q3
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; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg
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tBL 14, $noreg, 0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def undef %0.dsub_0:dquad, implicit-def undef %1.dsub_2:dquad
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tBX_RET 14, $noreg
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...
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