derek.holloway
7502bf64a4
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58 lines
1.6 KiB
LLVM
58 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=hexagon < %s | FileCheck %s
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; Check that we generate load instructions with global + offset
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%s.0 = type { i8, i8, i16, i32 }
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@g0 = common global %s.0 zeroinitializer, align 4
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; CHECK-LABEL: f0:
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; CHECK: r{{[0-9]+}} = memw(##g0+4)
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define void @f0(i32 %a0, i32 %a1, ptr nocapture %a2) #0 {
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b0:
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%v0 = icmp sgt i32 %a0, %a1
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br i1 %v0, label %b1, label %b2
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b1: ; preds = %b0
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%v1 = load i32, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 3), align 4
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store i32 %v1, ptr %a2, align 4
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br label %b2
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b2: ; preds = %b1, %b0
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ret void
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}
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; CHECK-LABEL: f1:
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; CHECK: r{{[0-9]+}} = memub(##g0+1)
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define void @f1(i32 %a0, i32 %a1, ptr nocapture %a2) #0 {
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b0:
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%v0 = icmp sgt i32 %a0, %a1
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br i1 %v0, label %b1, label %b2
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b1: ; preds = %b0
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%v1 = load i8, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 1), align 1
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store i8 %v1, ptr %a2, align 1
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br label %b2
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b2: ; preds = %b1, %b0
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ret void
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}
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; CHECK-LABEL: f2:
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; CHECK: r{{[0-9]+}} = memuh(##g0+2)
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define void @f2(i32 %a0, i32 %a1, ptr %a2) #0 {
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b0:
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%v0 = icmp sgt i32 %a0, %a1
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br i1 %v0, label %b1, label %b2
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b1: ; preds = %b0
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%v1 = load i16, ptr getelementptr inbounds (%s.0, ptr @g0, i32 0, i32 2), align 2
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store i16 %v1, ptr %a2, align 2
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br label %b2
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b2: ; preds = %b1, %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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