derek.holloway
7502bf64a4
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41 lines
1.7 KiB
LLVM
41 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=mips < %s -debug 2>&1 | FileCheck %s --check-prefix=MIPS
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; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot < %s \
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; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MIPS-XGOT
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; RUN: llc -mtriple=mips -mattr=+micromips < %s -debug 2>&1 | FileCheck %s --check-prefix=MM
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; RUN: llc -mtriple=mips -relocation-model=pic -mattr=+xgot,+micromips < %s \
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; RUN: -debug 2>&1 | FileCheck %s --check-prefix=MM-XGOT
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; REQUIRES: asserts
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; Tests that the correct ISA is selected for computing a global address.
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@x = global i32 0
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@a = global i32 1
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declare i32 @y(ptr, i32)
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define i32 @z() {
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entry:
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%0 = load i32, ptr @a, align 4
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%1 = call i32 @y(ptr @x, i32 %0)
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ret i32 %1
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}
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; MIPS-LABEL: ===== Instruction selection ends:
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; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<ptr @x> 0 [TF=4]
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; MIPS: t{{.*}}: i32 = ADDiu t[[A]], TargetGlobalAddress:i32<ptr @x> 0 [TF=5]
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; MIPS-XGOT-LABEL: ===== Instruction selection ends:
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; MIPS-XGOT: t[[B:[0-9]+]]: i32 = LUi TargetGlobalAddress:i32<ptr @x> 0 [TF=20]
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; MIPS-XGOT: t[[C:[0-9]+]]: i32 = ADDu t[[B]], Register:i32 %0
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; MIPS-XGOT: t{{.*}}: i32,ch = LW<Mem:(load (s32) from got)> t[[C]], TargetGlobalAddress:i32<ptr @x> 0 [TF=21], t{{.*}}
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; MM-LABEL: ===== Instruction selection ends:
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; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<ptr @x> 0 [TF=4]
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; MM: t{{.*}}: i32 = ADDiu_MM t[[A]], TargetGlobalAddress:i32<ptr @x> 0 [TF=5]
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; MM-XGOT-LABEL: ===== Instruction selection ends:
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; MM-XGOT: t[[B:[0-9]+]]: i32 = LUi_MM TargetGlobalAddress:i32<ptr @x> 0 [TF=20]
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; MM-XGOT: t[[C:[0-9]+]]: i32 = ADDU16_MM t[[B]], Register:i32 %0
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; MM-XGOT: t{{.*}}: i32,ch = LW_MM<Mem:(load (s32) from got)> t[[C]], TargetGlobalAddress:i32<ptr @x> 0 [TF=21], t0
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